文件名称:DDR3_user_design
介绍说明－－下载内容均来自于网络，请自行研究使用
在Xilinx开发环境ISE13.2上用MIG产生的DDR3 SDRAM控制器，里面生成了Core，可用于DDR3读写控制-On the Xilinx development environment ISE13.2 generated with MIG DDR3 SDRAM controller, which generates the Core, DDR3 can be used to read and write control
(系统自动生成,下载前可以参看下载内容)
下载文件列表
user_design
...........\datasheet.txt
...........\log.txt
...........\mig.cgc
...........\mig.prj
...........\par
...........\...\create_ise.bat
...........\...\DDR3_Design.cdc
...........\...\DDR3_Design.ucf
...........\...\icon_coregen.xco
...........\...\ila_coregen.xco
...........\...\ise_flow.bat
...........\...\ise_run.txt
...........\...\makeproj.bat
...........\...\mem_interface_top.ut
...........\...\readme.txt
...........\...\rem_files.bat
...........\...\set_ise_prop.tcl
...........\...\vio_coregen.xco
...........\rtl
...........\...\DDR3_Design.v
...........\...\infrastructure.v
...........\...\mcb_controller
...........\...\..............\iodrp_controller.v
...........\...\..............\iodrp_mcb_controller.v
...........\...\..............\mcb_raw_wrapper.v
...........\...\..............\mcb_soft_calibration.v
...........\...\..............\mcb_soft_calibration_top.v
...........\...\..............\mcb_ui_top.v
...........\...\memc_wrapper.v
...........\sim
...........\...\afifo.v
...........\...\cmd_gen.v
...........\...\cmd_prbs_gen.v
...........\...\data_prbs_gen.v
...........\...\DDR3_Design.prj
...........\...\ddr3_model_c4.v
...........\...\ddr3_model_parameters_c4.vh
...........\...\init_mem_pattern_ctr.v
...........\...\isim.bat
...........\...\isim.tcl
...........\...\mcb_flow_control.v
...........\...\mcb_traffic_gen.v
...........\...\memc_tb_top.v
...........\...\rd_data_gen.v
...........\...\readme.txt
...........\...\read_data_path.v
...........\...\read_posted_fifo.v
...........\...\sim.do
...........\...\sim_tb_top.v
...........\...\sp6_data_gen.v
...........\...\tg_status.v
...........\...\v6_data_gen.v
...........\...\write_data_path.v
...........\...\wr_data_gen.v
...........\synth
...........\.....\DDR3_Design.lso
...........\.....\DDR3_Design.prj
...........\.....\mem_interface_top_synp.sdc
...........\.....\script_synp.tcl
...........\tmp
...........\...\_cg
...........\...\...\xil_2516_5.in
...........\...\...\xil_2516_5.out
...........\datasheet.txt
...........\log.txt
...........\mig.cgc
...........\mig.prj
...........\par
...........\...\create_ise.bat
...........\...\DDR3_Design.cdc
...........\...\DDR3_Design.ucf
...........\...\icon_coregen.xco
...........\...\ila_coregen.xco
...........\...\ise_flow.bat
...........\...\ise_run.txt
...........\...\makeproj.bat
...........\...\mem_interface_top.ut
...........\...\readme.txt
...........\...\rem_files.bat
...........\...\set_ise_prop.tcl
...........\...\vio_coregen.xco
...........\rtl
...........\...\DDR3_Design.v
...........\...\infrastructure.v
...........\...\mcb_controller
...........\...\..............\iodrp_controller.v
...........\...\..............\iodrp_mcb_controller.v
...........\...\..............\mcb_raw_wrapper.v
...........\...\..............\mcb_soft_calibration.v
...........\...\..............\mcb_soft_calibration_top.v
...........\...\..............\mcb_ui_top.v
...........\...\memc_wrapper.v
...........\sim
...........\...\afifo.v
...........\...\cmd_gen.v
...........\...\cmd_prbs_gen.v
...........\...\data_prbs_gen.v
...........\...\DDR3_Design.prj
...........\...\ddr3_model_c4.v
...........\...\ddr3_model_parameters_c4.vh
...........\...\init_mem_pattern_ctr.v
...........\...\isim.bat
...........\...\isim.tcl
...........\...\mcb_flow_control.v
...........\...\mcb_traffic_gen.v
...........\...\memc_tb_top.v
...........\...\rd_data_gen.v
...........\...\readme.txt
...........\...\read_data_path.v
...........\...\read_posted_fifo.v
...........\...\sim.do
...........\...\sim_tb_top.v
...........\...\sp6_data_gen.v
...........\...\tg_status.v
...........\...\v6_data_gen.v
...........\...\write_data_path.v
...........\...\wr_data_gen.v
...........\synth
...........\.....\DDR3_Design.lso
...........\.....\DDR3_Design.prj
...........\.....\mem_interface_top_synp.sdc
...........\.....\script_synp.tcl
...........\tmp
...........\...\_cg
...........\...\...\xil_2516_5.in
...........\...\...\xil_2516_5.out