文件名称:PipelineSim
介绍说明－－下载内容均来自于网络，请自行研究使用
一个计算机原理课程设计的作业，5级流水线CPU，指令集到代码均为自己设计，有最终报告文档，组建说明，并行除法，16位字长，定长指令，Verilog源代码，顶层设计图。结构简单，冲突解决方式也很简单，代码量小。-A computer theory course design work, five pipelined CPU, instruction set to the code are design, the final report documents the formation of parallel division, 16-bit word length, fixed-length instructions, Verilog source code, top level design. Simple structure, conflict resolution is also very simple, a small amount of code.
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下载文件列表
PipelineSim\ALU.v
...........\decoder.v
...........\IF.v
...........\MemInterface.v
...........\Pipeline.v
...........\PipelineSim.cr.mti
...........\PipelineSim.mpf
...........\RegisterFile.v
...........\Simulate.v
...........\transcript
...........\vsim.wlf
...........\WB.v
...........\work\@a@l@u\verilog.asm
...........\....\......\_primary.dat
...........\....\......\_primary.vhd
...........\....\.inst@decoder\verilog.asm
...........\....\.............\_primary.dat
...........\....\.............\_primary.vhd
...........\....\......fetch\verilog.asm
...........\....\...........\_primary.dat
...........\....\...........\_primary.vhd
...........\....\.mem@interface\verilog.asm
...........\....\..............\_primary.dat
...........\....\..............\_primary.vhd
...........\....\.pipeline\verilog.asm
...........\....\.........\_primary.dat
...........\....\.........\_primary.vhd
...........\....\.register@file\verilog.asm
...........\....\..............\_primary.dat
...........\....\..............\_primary.vhd
...........\....\.simulate\verilog.asm
...........\....\.........\_primary.dat
...........\....\.........\_primary.vhd
...........\....\.write@back\verilog.asm
...........\....\...........\_primary.dat
...........\....\...........\_primary.vhd
...........\....\ALU.v
...........\....\decoder.v
...........\....\IF.v
...........\....\MemInterface.v
...........\....\Pipeline.v
...........\....\RegisterFile.v
...........\....\Simulate.v
...........\....\WB.v
...........\....\_info
...........\....\@a@l@u
...........\....\@inst@decoder
...........\....\@inst@fetch
...........\....\@mem@interface
...........\....\@pipeline
...........\....\@register@file
...........\....\@simulate
...........\....\@write@back
...........\work
PipelineSim
...........\decoder.v
...........\IF.v
...........\MemInterface.v
...........\Pipeline.v
...........\PipelineSim.cr.mti
...........\PipelineSim.mpf
...........\RegisterFile.v
...........\Simulate.v
...........\transcript
...........\vsim.wlf
...........\WB.v
...........\work\@a@l@u\verilog.asm
...........\....\......\_primary.dat
...........\....\......\_primary.vhd
...........\....\.inst@decoder\verilog.asm
...........\....\.............\_primary.dat
...........\....\.............\_primary.vhd
...........\....\......fetch\verilog.asm
...........\....\...........\_primary.dat
...........\....\...........\_primary.vhd
...........\....\.mem@interface\verilog.asm
...........\....\..............\_primary.dat
...........\....\..............\_primary.vhd
...........\....\.pipeline\verilog.asm
...........\....\.........\_primary.dat
...........\....\.........\_primary.vhd
...........\....\.register@file\verilog.asm
...........\....\..............\_primary.dat
...........\....\..............\_primary.vhd
...........\....\.simulate\verilog.asm
...........\....\.........\_primary.dat
...........\....\.........\_primary.vhd
...........\....\.write@back\verilog.asm
...........\....\...........\_primary.dat
...........\....\...........\_primary.vhd
...........\....\ALU.v
...........\....\decoder.v
...........\....\IF.v
...........\....\MemInterface.v
...........\....\Pipeline.v
...........\....\RegisterFile.v
...........\....\Simulate.v
...........\....\WB.v
...........\....\_info
...........\....\@a@l@u
...........\....\@inst@decoder
...........\....\@inst@fetch
...........\....\@mem@interface
...........\....\@pipeline
...........\....\@register@file
...........\....\@simulate
...........\....\@write@back
...........\work
PipelineSim