文件名称:VerilogHDL
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《设计与验证Verilog HDL》光盘内容
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压缩包 : 63535326veriloghdl.rar 列表 设计与验证Verilog HDL\Example-7-1\示例说明.doc 设计与验证Verilog HDL\Example-7-2\示例说明.doc 设计与验证Verilog HDL\Example-7-3\示例说明.doc 设计与验证Verilog HDL\Example-7-4\示例说明.doc 设计与验证Verilog HDL\Example-8-1\示例说明.doc 设计与验证Verilog HDL\Example-8-2\示例说明.doc 设计与验证Verilog HDL\Example-4-10\示例说明.doc 设计与验证Verilog HDL\Example-5-6\示例说明.doc 设计与验证Verilog HDL\Example-5-7\示例说明.doc 设计与验证Verilog HDL\Example-5-8\示例说明.doc 设计与验证Verilog HDL\Example-4-13\示例说明.doc 设计与验证Verilog HDL\Example-4-16\示例说明.doc 设计与验证Verilog HDL\Example-4-11\示例说明.doc 设计与验证Verilog HDL\Example-4-20\示例说明.doc 设计与验证Verilog HDL\Example-4-7\示例说明.doc 设计与验证Verilog HDL\Example-4-8\示例说明.doc 设计与验证Verilog HDL\Example-5-1\示例说明.doc 设计与验证Verilog HDL\Example-5-5\示例说明.doc 设计与验证Verilog HDL\Example-4-1\示例说明.doc 设计与验证Verilog HDL\Example-4-14\示例说明.doc 设计与验证Verilog HDL\Example-4-4\示例说明.doc 设计与验证Verilog HDL\Example-4-17\示例说明.doc 设计与验证Verilog HDL\Example-4-21\示例说明.doc 设计与验证Verilog HDL\Example-6-1\示例说明.doc 设计与验证Verilog HDL\Example-6-1\FSM\state_default\rev_2\CS.txt 设计与验证Verilog HDL\Example-6-1\FSM\state2\rev_1\CS.txt 设计与验证Verilog HDL\Example-6-1\FSM\state3\rev_2\CS.txt 设计与验证Verilog HDL\Example-6-1\FSM\state1\rev_1\NS.txt 设计与验证Verilog HDL\Example-7-2\Proj\Read_In_File.txt 设计与验证Verilog HDL\Example-7-3\Proj\Read_In_File.txt 设计与验证Verilog HDL\Example-7-4\Proj\Read_In_File.txt 设计与验证Verilog HDL\Example-7-2\Proj\Testbench_readme.txt 设计与验证Verilog HDL\Example-7-1\Proj\Testbench_readme.txt 设计与验证Verilog HDL\Example-4-20\case\PrecisionRTL\case_impl_1\unfolded_operators.txt 设计与验证Verilog HDL\Example-4-20\decode\case\decode_case_impl_1\unfolded_operators.txt 设计与验证Verilog HDL\Example-4-20\decode\if_mult\precision_impl_1\unfolded_operators.txt 设计与验证Verilog HDL\Example-4-20\decode\if_single\precision_impl_1\unfolded_operators.txt 设计与验证Verilog HDL\Example-4-20\if_mult\PrecisionRTL\if_mult_impl_1\unfolded_operators.txt 设计与验证Verilog HDL\Example-4-20\if_single\PrecisionRTL\if_single_impl_1\unfolded_operators.txt 设计与验证Verilog HDL\Example-4-10\bibus\rev_1\rpt_bibus_areasrr.htm 设计与验证Verilog HDL\Example-4-14\clk_div_phase\rev_1\rpt_clk_div_phase_areasrr.htm 设计与验证Verilog HDL\Example-4-10\complex_bibus\rev_1\rpt_complex_bibus_areasrr.htm 设计与验证Verilog HDL\Example-5-5\rev_2\rpt_latch_areasrr.htm 设计与验证Verilog HDL\Example-4-11\rev_1\rpt_mux_areasrr.htm 设计与验证Verilog HDL\Example-4-13\ram_basic\rev_2\rpt_ram_basic_areasrr.htm 设计与验证Verilog HDL\Example-4-4\rev_2\rpt_reg_counter_areasrr.htm 设计与验证Verilog HDL\Example-5-6\rev_1\rpt_resource_share1_areasrr.htm 设计与验证Verilog HDL\Example-5-6\rev_1\rpt_resource_share2_areasrr.htm 设计与验证Verilog HDL\Example-5-8\rev_2\rpt_shannon_fast_areasrr.htm 设计与验证Verilog HDL\Example-4-16\rev_1\rpt_srl2pal_areasrr.htm 设计与验证Verilog HDL\Example-6-1\FSM\state2\rev_1\rpt_state2_areasrr.htm 设计与验证Verilog HDL\Example-5-8\rev_2\rpt_un_shannon_areasrr.htm 设计与验证Verilog HDL\Example-4-20\case\PrecisionRTL\case_impl_1\rtlc.out\INCR\incr_driver.log 设计与验证Verilog HDL\Example-4-20\decode\case\decode_case_impl_1\rtlc.out\INCR\incr_driver.log 设计与验证Verilog HDL\Example-4-20\decode\if_mult\precision_impl_1\rtlc.out\INCR\incr_driver.log 设计与验证Verilog HDL\Example-4-20\decode\if_single\precision_impl_1\rtlc.out\INCR\incr_driver.log 设计与验证Verilog HDL\Example-4-20\if_mult\PrecisionRTL\if_mult_impl_1\rtlc.out\INCR\incr_driver.log 设计与验证Verilog HDL\Example-4-20\if_single\PrecisionRTL\if_single_impl_1\rtlc.out\INCR\incr_driver.log 设计与验证Verilog HDL\Example-4-20\case\PrecisionRTL\case_impl_1\rtlc.out\INCR\incr_rtlc.log 设计与验证Verilog HDL\Example-4-20\decode\case\decode_case_impl_1\rtlc.out\INCR\incr_rtlc.log 设计与验证Verilog HDL\Example-4-20\decode\if_mult\precision_impl_1\rtlc.out\INCR\incr_rtlc.log 设计与验证Verilog HDL\Example-4-20\decode\if_single\precision_impl_1\rtlc.out\INCR\incr_rtlc.log 设计与验证Verilog HDL\Example-4-20\if_mult\PrecisionRTL\if_mult_impl_1\rtlc.out\INCR\incr_rtlc.log 设计与验证Verilog HDL\Example-4-20\if_single\PrecisionRTL\if_single_impl_1\rtlc.out\INCR\incr_rtlc.log 设计与验证Verilog HDL\Example-4-20\decode\if_mult\precision_impl_1\precision.log 设计与验证Verilog HDL\Example-4-20\case\PrecisionRTL\case_impl_1\precision.log 设计与验证Verilog HDL\Example-4-20\if_mult\PrecisionRTL\if_mult_impl_1\precision.log 设计与验证Verilog HDL\Example-4-20\decode\case\decode_case_impl_1\precision.log 设计与验证Verilog HDL\Example-4-20\if_single\PrecisionRTL\if_single_impl_1\precision.log 设计与验证Verilog HDL\Example-4-20\decode\if_single\precision_impl_1\precision.log 设计与验证Verilog HDL\Example-4-20\decode\if_single\precision.log 设计与验证Verilog HDL\Example-4-14\clk_3div\sim\work\clk_3div_tb\verilog.asm 设计与验证Verilog HDL\Example-4-14\clk_3div\sim\work\clk_3div\verilog.asm 设计与验证Verilog HDL\Example-4-14\clk_div_phase\sim\work\clk_div_phase\verilog.asm 设计与验证Verilog HDL\Example-4-14\clk_div_phase\sim\work\clk_div_phase_tb\verilog.asm 设计与验证Verilog HDL\Example-4-7\sim\work\clock_edge_tb\verilog.asm 设计与验证Verilog HDL\Example-4-13\sim\work\ram_basic\verilog.asm 设计与验证Verilog HDL\Example-4-7\sim\work\clock_edge\verilog.asm 设计与验证Verilog HDL\Example-4-8\sim\work\decode_cmb_tb\verilog.asm 设计与验证Verilog HDL\Example-4-8\sim\work\decode_cmb\verilog.asm 设计与验证Verilog HDL\Example-4-8\sim\work\decode_cmb2\verilog.asm 设计与验证Verilog HDL\Example-4-13\sim\work\ram_basic_tb\verilog.asm 设计与验证Verilog HDL\Example-4-20\case\PrecisionRTL\case_RTL_schematic.bmp 设计与验证Verilog HDL\Example-4-20\case\SynplifyPro\case_rtl_view.bmp 设计与验证Verilog HDL\Example-4-20\case\PrecisionRTL\case_schematic.bmp 设计与验证Verilog HDL\Example-4-20\case\SynplifyPro\case_tech_view.bmp 设计与验证Verilog HDL\Example-5-1\FHTPART_resource.bmp 设计与验证Verilog HDL\Example-4-20\decode\if_mult\if_mult_decode_RTL_veiw.bmp 设计与验证Verilog HDL\Example-4-20\decode\if_mult\if_mult_decode_tech_veiw.bmp 设计与验证Verilog HDL\Example-4-20\decode\if_mult\if_mult_RTL_schematic.bmp 设计与验证Verilog HDL\Example-4-20\if_mult\PrecisionRTL\if_mult_RTL_schematic.bmp 设计与验证Verilog HDL\Example-4-20\if_mult\SynplifyPro\if_mult_rtl_view.bmp 设计与验证Verilog HDL\Example-4-20\if_mult\PrecisionRTL\if_mult_schematic.bmp 设计与验证Verilog HDL\Example-4-20\decode\if_mult\if_mult_schematic.bmp 设计与验证Verilog HDL\Example-4-20\if_mult\SynplifyPro\if_mult_tech_view.bmp 设计与验证Verilog HDL\Example-4-20\decode\if_single\if_single_decode_RTL_view.bmp 设计与验证Verilog HDL\Example-4-20\decode\if_single\if_single_decode_tech_view.bmp 设计与验证Verilog HDL\Example-4-20\if_single\PrecisionRTL\if_single_RTL_schemaitc.bmp 设计与验证Verilog HDL\Example-4-20\decode\if_single\if_single_RTL_schematic.bmp 设计与验证Verilog HDL\Example-4-20\if_single\SynplifyPro\if_single_rtl_view.bmp 设计与验证Verilog HDL\Example-4-20\if_single\PrecisionRTL\if_single_schematic.bmp 设计与验证Verilog HDL\Example-4-20\decode\if_single\if_single_schematic.bmp 设计与验证Verilog HDL\Example-4-20\if_single\SynplifyPro\if_single_tech_view.bmp 设计与验证Verilog HDL\Example-4-20\if_mult\Latch_if_mult\Latch_Synplify_RTL_view.bmp 设计与验证Verilog HDL\Example-4-20\if_mult\Latch_if_mult\Latch_Synplify_tech_view.bmp 设计与验证Verilog HDL\Example-4-20\decode\case\precision_RTL_schematic.bmp 设计与验证Verilog HDL\Example-4-20\decode\case\precision_schematic.bmp 设计与验证Verilog HDL\Example-4-20\decode\case\synplify_rtl_view.bmp 设计与验证Verilog HDL\Example-4-20\decode\case\synplify_tech_view.bmp 设计与验证Verilog HDL\Example-5-1\wchfht_resource.bmp 设计与验证Verilog HDL\Example-4-13\sim\work\_info 设计与验证Verilog HDL\Example-4-7\sim\work\_info 设计与验证Verilog HDL\Example-4-14\clk_3div\sim\work\_info 设计与验证Verilog HDL\Example-4-14\clk_div_phase\sim\work\_info 设计与验证Verilog HDL\Example-4-8\sim\work\_info 设计与验证Verilog HDL\Example-4-20\decode\case\decode_case_impl_1\hdlAnalyze_verilogfile 设计与验证Verilog HDL\Example-4-20\case\PrecisionRTL\case_impl_1\hdlAnalyze_verilogfile 设计与验证Verilog HDL\Example-4-20\decode\if_mult\precision_impl_1\hdlAnalyze_verilogfile 设计与验证Verilog HDL\Example-4-20\if_mult\PrecisionRTL\if_mult_impl_1\hdlAnalyze_verilogfile 设计与验证Verilog HDL\Example-4-20\decode\if_single\precision_impl_1\hdlAnalyze_verilogfile 设计与验证Verilog HDL\Example-4-20\if_single\PrecisionRTL\if_single_impl_1\hdlAnalyze_verilogfile 设计与验证Verilog HDL\Example-4-20\case\PrecisionRTL\case_impl_1\rtlc_libs\work\rtlc_version_info 设计与验证Verilog HDL\Example-4-20\decode\case\decode_case_impl_1\rtlc_libs\work\rtlc_version_info 设计与验证Verilog HDL\Example-4-20\decode\if_mult\precision_impl_1\rtlc_libs\work\rtlc_version_info 设计与验证Verilog HDL\Example-4-20\decode\if_single\precision_impl_1\rtlc_libs\work\rtlc_version_info 设计与验证Verilog HDL\Example-4-20\if_mult\PrecisionRTL\if_mult_impl_1\rtlc_libs\work\rtlc_version_info 设计与验证Verilog HDL\Example-4-20\if_single\PrecisionRTL\if_single_impl_1\rtlc_libs\work\rtlc_version_info 设计与验证Verilog HDL\Example-3-1\transcript 设计与验证Verilog HDL\Example-4-8\sim\transcript 设计与验证Verilog HDL\Example-4-7\sim\transcript 设计与验证Verilog HDL\Example-4-13\sim\transcript 设计与验证Verilog HDL\Example-4-14\clk_div_phase\sim\transcript 设计与验证Verilog HDL\Example-4-10\bibus\rev_1\rpt_bibus.areasrr 设计与验证Verilog HDL\Example-4-14\clk_div_phase\rev_1\rpt_clk_div_phase.areasrr 设计与验证Verilog HDL\Example-4-10\complex_bibus\rev_1\rpt_complex_bibus.areasrr 设计与验证Verilog HDL\Example-5-5\rev_2\rpt_latch.areasrr 设计与验证Verilog HDL\Example-4-11\rev_1\rpt_mux.areasrr 设计与验证Verilog HDL\Example-4-13\ram_basic\rev_2\rpt_ram_basic.areasrr 设计与验证Verilog HDL\Example-4-4\rev_2\rpt_reg_counter.areasrr 设计与验证Verilog HDL\Example-5-6\rev_1\rpt_resource_share1.areasrr 设计与验证Verilog HDL\Example-5-6\rev_1\rpt_resource_share2.areasrr 设计与验证Verilog HDL\Example-5-8\rev_2\rpt_shannon_fast.areasrr 设计与验证Verilog HDL\Example-4-16\rev_1\rpt_srl2pal.areasrr 设计与验证Verilog HDL\Example-6-1\FSM\state2\rev_1\rpt_state2.areasrr 设计与验证Verilog HDL\Example-5-8\rev_2\rpt_un_shannon.areasrr 设计与验证Verilog HDL\Example-4-20\case\PrecisionRTL\case_impl_1\rtlc.out\rtlc.args 设计与验证Verilog HDL\Example-4-20\decode\case\decode_case_impl_1\rtlc.out\rtlc.args 设计与验证Verilog HDL\Example-4-20\if_mult\PrecisionRTL\if_mult_impl_1\rtlc.out\rtlc.args 设计与验证Verilog HDL\Example-4-20\decode\if_mult\precision_impl_1\rtlc.out\rtlc.args 设计与验证Verilog HDL\Example-4-20\if_single\PrecisionRTL\if_single_impl_1\rtlc.out\rtlc.args 设计与验证Verilog HDL\Example-4-20\decode\if_single\precision_impl_1\rtlc.out\rtlc.args 设计与验证Verilog HDL\Example-4-20\decode\case\decode_case_impl_1\rtlc_libs\work\case_decode.mod.body 设计与验证Verilog HDL\Example-4-20\case\PrecisionRTL\case_impl_1\rtlc_libs\work\case1.mod.body 设计与验证Verilog HDL\Example-4-20\decode\if_mult\precision_impl_1\rtlc_libs\work\if_mult_decode.mod.body 设计与验证Verilog HDL\Example-4-20\decode\if_single\precision_impl_1\rtlc_libs\work\if_single_decode.mod.body 设计与验证Verilog HDL\Example-4-20\if_mult\PrecisionRTL\if_mult_impl_1\rtlc_libs\work\mult_if.mod.body 设计与验证Verilog HDL\Example-4-20\if_single\PrecisionRTL\if_single_impl_1\rtlc_libs\work\single_if.mod.body 设计与验证Verilog HDL\Example-4-20\case\PrecisionRTL\case_impl_1\rtlc.out\autotop.conf 设计与验证Verilog HDL\Example-4-20\decode\case\decode_case_impl_1\rtlc.out\autotop.conf 设计与验证Verilog HDL\Example-4-20\if_mult\PrecisionRTL\if_mult_impl_1\rtlc.out\autotop.conf 设计与验证Verilog HDL\Example-4-20\decode\if_mult\precision_impl_1\rtlc.out\autotop.conf 设计与验证Verilog HDL\Example-4-20\if_single\PrecisionRTL\if_single_impl_1\rtlc.out\autotop.conf 设计与验证Verilog HDL\Example-4-20\decode\if_single\precision_impl_1\rtlc.out\autotop.conf 设计与验证Verilog HDL\Example-4-14\clk_3div\sim\work\clk_3div_tb\_primary.dat 设计与验证Verilog HDL\Example-4-14\clk_div_phase\sim\work\clk_div_phase\_primary.dat 设计与验证Verilog HDL\Example-4-14\clk_div_phase\sim\work\clk_div_phase_tb\_primary.dat 设计与验证Verilog HDL\Example-4-7\sim\work\clock_edge_tb\_primary.dat 设计与验证Verilog HDL\Example-4-14\clk_3div\sim\work\clk_3div\_primary.dat 设计与验证Verilog HDL\Example-4-7\sim\work\clock_edge\_primary.dat 设计与验证Verilog HDL\Example-4-13\sim\work\ram_basic\_primary.dat 设计与验证Verilog HDL\Example-4-8\sim\work\decode_cmb2\_primary.dat 设计与验证Verilog HDL\Example-4-8\sim\work\decode_cmb\_primary.dat 设计与验证Verilog HDL\Example-4-8\sim\work\decode_cmb_tb\_primary.dat 设计与验证Verilog HDL\Example-4-13\sim\work\ram_basic_tb\_primary.dat 设计与验证Verilog HDL\Example-4-20\case\PrecisionRTL\case_impl_1\rtlc.out\legalmodmap.db 设计与验证Verilog HDL\Example-4-20\if_mult\PrecisionRTL\if_mult_impl_1\rtlc.out\legalmodmap.db 设计与验证Verilog HDL\Example-4-20\if_single\PrecisionRTL\if_single_impl_1\rtlc.out\legalmodmap.db 设计与验证Verilog HDL\Example-4-20\decode\case\decode_case_impl_1\rtlc.out\legalmodmap.db 设计与验证Verilog HDL\Example-4-20\decode\if_mult\precision_impl_1\rtlc.out\legalmodmap.db 设计与验证Verilog HDL\Example-4-20\decode\if_single\precision_impl_1\rtlc.out\legalmodmap.db 设计与验证Verilog HDL\Example-4-20\case\PrecisionRTL\Thumbs.db 设计与验证Verilog HDL\Example-4-20\if_mult\PrecisionRTL\Thumbs.db 设计与验证Verilog HDL\Example-4-20\if_single\PrecisionRTL\Thumbs.db 设计与验证Verilog HDL\Example-4-20\case\SynplifyPro\Thumbs.db 设计与验证Verilog HDL\Example-5-1\Thumbs.db 设计与验证Verilog HDL\Example-8-1\sim\sim.do 设计与验证Verilog HDL\Example-8-2\Blocking_LHS_Delay\sim.do 设计与验证Verilog HDL\Example-8-2\Blocking_RHS_Delay\sim.do 设计与验证Verilog HDL\Example-8-2\NonBlocking_LHS_Delay\sim.do 设计与验证Verilog HDL\Example-8-2\NonBlocking_RHS_Delay\sim.do 设计与验证Verilog HDL\Example-7-1\Proj\sim.do 设计与验证Verilog HDL\Example-7-2\Proj\sim.do 设计与验证Verilog HDL\Example-7-3\Proj\sim.do 设计与验证Verilog HDL\Example-7-4\Proj\Sim.do 设计与验证Verilog HDL\Example-8-2\Blocking_LHS_Delay\wave.do 设计与验证Verilog HDL\Example-8-2\Blocking_RHS_Delay\wave.do 设计与验证Verilog HDL\Example-8-2\NonBlocking_LHS_Delay\wave.do 设计与验证Verilog HDL\Example-8-2\NonBlocking_RHS_Delay\wave.do 设计与验证Verilog HDL\Example-7-4\Proj\wave.do 设计与验证Verilog HDL\Example-4-14\clk_div_phase\sim\wave.do 设计与验证Verilog HDL\Example-7-3\Proj\wave.do 设计与验证Verilog HDL\Example-7-1\Proj\wave.do 设计与验证Verilog HDL\Example-7-2\Proj\wave.do 设计与验证Verilog HDL\Example-4-14\clk_3div\sim\wave.do 设计与验证Verilog HDL\Example-4-7\sim\wave.do 设计与验证Verilog HDL\Example-4-13\sim\wave.do 设计与验证Verilog HDL\Example-4-20\decode\case\decode_case_impl_1\case_decode.edf 设计与验证Verilog HDL\Example-4-20\case\PrecisionRTL\case_impl_1\case1.edf 设计与验证Verilog HDL\Example-4-14\clk_3div\synthesis\rev_1\clk_3div.edf 设计与验证Verilog HDL\Example-4-14\clk_div_phase\rev_1\clk_div_phase.edf 设计与验证Verilog HDL\Example-4-1\rev_1\cnt1.edf 设计与验证Verilog HDL\Example-4-1\rev_1\cnt2.edf 设计与验证Verilog HDL\Example-4-1\rev_1\cnt3.edf 设计与验证Verilog HDL\Example-4-20\decode\if_mult\precision_impl_1\if_mult_decode.edf 设计与验证Verilog HDL\Example-4-20\decode\if_single\precision_impl_1\if_single_decode.edf 设计与验证Verilog HDL\Example-5-5\rev_2\latch.edf 设计与验证Verilog HDL\Example-4-20\if_mult\PrecisionRTL\if_mult_impl_1\mult_if.edf 设计与验证Verilog HDL\Example-4-11\rev_1\mux.edf 设计与验证Verilog HDL\Example-4-11\rev_1\mux2.edf 设计与验证Verilog HDL\Example-4-13\ram_basic\rev_2\ram_basic.edf 设计与验证Verilog HDL\Example-4-4\rev_2\reg_counter.edf 设计与验证Verilog HDL\Example-4-20\if_single\PrecisionRTL\if_single_impl_1\single_if.edf 设计与验证Verilog HDL\Example-4-16\rev_1\srl2pal.edf 设计与验证Verilog HDL\Example-4-17\asyn_rst\rev_1\asyn_rst.edn 设计与验证Verilog HDL\Example-4-20\decode\case\rev_1\case_decode.edn 设计与验证Verilog HDL\Example-4-20\case\SynplifyPro\rev_2\case1.edn 设计与验证Verilog HDL\Example-4-7\rev_2\clock_edge.edn 设计与验证Verilog HDL\Example-4-21\asyn_bad\rev_1\decode.edn 设计与验证Verilog HDL\Example-4-8\rev_2\decode_cmb.edn 设计与验证Verilog HDL\Example-4-8\rev_2\decode_cmb2.edn 设计与验证Verilog HDL\Example-4-20\decode\if_mult\rev_2\if_mult_decode.edn 设计与验证Verilog HDL\Example-4-20\decode\if_single\rev_1\if_single_decode.edn 设计与验证Verilog HDL\Example-4-20\if_mult\Latch_if_mult\rev_2\latch_mult_if.edn 设计与验证Verilog HDL\Example-5-7\rev_1\mod_copy1.edn 设计与验证Verilog HDL\Example-5-7\rev_1\mod_copy2.edn 设计与验证Verilog HDL\Example-4-20\if_mult\SynplifyPro\rev_1\mult_if.edn 设计与验证Verilog HDL\Example-4-11\rev_1\mux.edn 设计与验证Verilog HDL\Example-4-20\if_single\SynplifyPro\rev_2\single_if.edn 设计与验证Verilog HDL\Example-6-1\FSM\state1\rev_1\state1.edn 设计与验证Verilog HDL\Example-6-1\FSM\state2\rev_1\state2.edn 设计与验证Verilog HDL\Example-6-1\FSM\state_default\rev_2\state2_default.edn 设计与验证Verilog HDL\Example-6-1\FSM\state3\rev_2\state3.edn 设计与验证Verilog HDL\Example-4-17\syn_rst\rev_2\syn_rst.edn 设计与验证Verilog HDL\Example-4-21\oe_edge\rev_2\top.edn 设计与验证Verilog HDL\Example-4-21\syn_wr\rev_1\top.edn 设计与验证Verilog HDL\Example-4-20\case\PrecisionRTL\case_impl_1\rtlc.out\rtlc_args1.file 设计与验证Verilog HDL\Example-4-20\if_mult\PrecisionRTL\if_mult_impl_1\rtlc.out\rtlc_args1.file 设计与验证Verilog HDL\Example-4-20\if_single\PrecisionRTL\if_single_impl_1\rtlc.out\rtlc_args1.file 设计与验证Verilog HDL\Example-4-20\decode\case\decode_case_impl_1\rtlc.out\rtlc_args1.file 设计与验证Verilog HDL\Example-4-20\decode\if_mult\precision_impl_1\rtlc.out\rtlc_args1.file 设计与验证Verilog HDL\Example-4-20\decode\if_single\precision_impl_1\rtlc.out\rtlc_args1.file 设计与验证Verilog HDL\Example-4-17\asyn_rst\rev_1\asyn_rst.fse 设计与验证Verilog HDL\Example-4-10\bibus\rev_1\bibus.fse 设计与验证Verilog HDL\Example-4-20\decode\case\rev_1\case_decode.fse 设计与验证Verilog HDL\Example-4-20\case\SynplifyPro\rev_2\case1.fse 设计与验证Verilog HDL\Example-4-14\clk_3div\synthesis\rev_1\clk_3div.fse 设计与验证Verilog HDL\Example-4-14\clk_div_phase\rev_1\clk_div_phase.fse 设计与验证Verilog HDL\Example-4-7\rev_2\clock_edge.fse 设计与验证Verilog HDL\Example-4-1\rev_1\cnt1.fse 设计与验证Verilog HDL\Example-4-1\rev_1\cnt2.fse 设计与验证Verilog HDL\Example-4-1\rev_1\cnt3.fse 设计与验证Verilog HDL\Example-4-10\complex_bibus\rev_1\complex_bibus.fse 设计与验证Verilog HDL\Example-4-10\complex_bibus\rev_1\complex_bibus2.fse 设计与验证Verilog HDL\Example-4-21\asyn_bad\rev_1\decode.fse 设计与验证Verilog HDL\Example-4-8\rev_2\decode_cmb.fse 设计与验证Verilog HDL\Example-4-8\rev_2\decode_cmb2.fse 设计与验证Verilog HDL\Example-5-1\before_optimized\rev_1\fhtpart.fse 设计与验证Verilog HDL\Example-4-11\rev_1\generic.fse 设计与验证Verilog HDL\Example-4-17\asyn_rst\rev_1\generic.fse 设计与验证Verilog HDL\Example-4-17\syn_rst\rev_2\generic.fse 设计与验证Verilog HDL\Example-4-20\case\SynplifyPro\rev_2\generic.fse 设计与验证Verilog HDL\Example-4-20\decode\case\rev_1\generic.fse 设计与验证Verilog HDL\Example-4-20\decode\if_mult\rev_2\generic.fse 设计与验证Verilog HDL\Example-4-20\decode\if_single\rev_1\generic.fse 设计与验证Verilog HDL\Example-4-20\if_mult\Latch_if_mult\rev_2\generic.fse 设计与验证Verilog HDL\Example-4-20\if_mult\SynplifyPro\rev_1\generic.fse 设计与验证Verilog HDL\Example-4-20\if_single\SynplifyPro\rev_2\generic.fse 设计与验证Verilog HDL\Example-4-21\asyn_bad\rev_1\generic.fse 设计与验证Verilog HDL\Example-4-21\oe_edge\rev_2\generic.fse 设计与验证Verilog HDL\Example-4-21\syn_wr\rev_1\generic.fse 设计与验证Verilog HDL\Example-4-7\rev_2\generic.fse 设计与验证Verilog HDL\Example-4-8\rev_2\generic.fse 设计与验证Verilog HDL\Example-5-7\rev_1\generic.fse 设计与验证Verilog HDL\Example-6-1\FSM\state_default\rev_2\generic.fse 设计与验证Verilog HDL\Example-6-1\FSM\state1\rev_1\generic.fse 设计与验证Verilog HDL\Example-6-1\FSM\state2\rev_1\generic.fse 设计与验证Verilog HDL\Example-6-1\FSM\state3\rev_2\generic.fse 设计与验证Verilog HDL\Example-4-20\decode\if_mult\rev_2\if_mult_decode.fse 设计与验证Verilog HDL\Example-4-20\decode\if_single\rev_1\if_single_decode.fse 设计与验证Verilog HDL\Example-5-5\rev_2\latch.fse 设计与验证Verilog HDL\Example-4-20\if_mult\Latch_if_mult\rev_2\latch_mult_if.fse 设计与验证Verilog HDL\Example-5-7\rev_1\mod_copy1.fse 设计与验证Verilog HDL\Example-5-7\rev_1\mod_copy2.fse 设计与验证Verilog HDL\Example-4-20\if_mult\SynplifyPro\rev_1\mult_if.fse 设计与验证Verilog HDL\Example-4-11\rev_1\mux.fse 设计与验证Verilog HDL\Example-4-11\rev_1\mux2.fse 设计与验证Verilog HDL\Example-4-13\ram_basic\rev_2\ram_basic.fse 设计与验证Verilog HDL\Example-4-4\rev_2\reg_counter.fse 设计与验证Verilog HDL\Example-5-6\rev_1\resource_share1.fse 设计与验证Verilog HDL\Example-5-6\rev_1\resource_share2.fse 设计与验证Verilog HDL\Example-5-8\rev_2\shannon_fast.fse 设计与验证Verilog HDL\Example-4-20\if_single\SynplifyPro\rev_2\single_if.fse 设计与验证Verilog HDL\Example-4-16\rev_1\srl2pal.fse 设计与验证Verilog HDL\Example-6-1\FSM\state1\rev_1\state1.fse 设计与验证Verilog HDL\Example-6-1\FSM\state2\rev_1\state2.fse 设计与验证Verilog HDL\Example-6-1\FSM\state_default\rev_2\state2_default.fse 设计与验证Verilog HDL\Example-6-1\FSM\state3\rev_2\state3.fse 设计与验证Verilog HDL\Example-4-17\syn_rst\rev_2\syn_rst.fse 设计与验证Verilog HDL\Example-4-21\oe_edge\rev_2\top.fse 设计与验证Verilog HDL\Example-4-21\syn_wr\rev_1\top.fse 设计与验证Verilog HDL\Example-5-8\rev_2\un_shannon.fse 设计与验证Verilog HDL\Example-5-1\after_optimized\rev_2\wch_fht.fse 设计与验证Verilog HDL\Example-6-1\FSM\state1\rev_1\fsmviewer.fsm 设计与验证Verilog HDL\Example-6-1\FSM\state3\rev_2\fsmviewer.fsm 设计与验证Verilog HDL\Example-6-1\FSM\state2\rev_1\fsmviewer.fsm 设计与验证Verilog HDL\Example-6-1\FSM\state_default\rev_2\fsmviewer.fsm 设计与验证Verilog HDL\Example-4-20\decode\case\decode_case_impl_1\case_decode_rtl.ixdb 设计与验证Verilog HDL\Example-4-20\case\PrecisionRTL\case_impl_1\case1_rtl.ixdb 设计与验证Verilog HDL\Example-4-20\decode\if_mult\precision_impl_1\if_mult_decode_rtl.ixdb 设计与验证Verilog HDL\Example-4-20\decode\if_single\precision_impl_1\if_single_decode_rtl.ixdb 设计与验证Verilog HDL\Example-4-20\if_mult\PrecisionRTL\if_mult_impl_1\mult_if_rtl.ixdb 设计与验证Verilog HDL\Example-4-20\if_single\PrecisionRTL\if_single_impl_1\single_if_rtl.ixdb 设计与验证Verilog HDL\Example-4-20\case\PrecisionRTL\case_impl_1\rtlc.out\INCR\emptymod.list 设计与验证Verilog HDL\Example-4-20\decode\case\decode_case_impl_1\rtlc.out\INCR\emptymod.list 设计与验证Verilog HDL\Example-4-20\decode\if_mult\precision_impl_1\rtlc.out\INCR\emptymod.list 设计与验证Verilog HDL\Example-4-20\decode\if_single\precision_impl_1\rtlc.out\INCR\emptymod.list 设计与验证Verilog HDL\Example-4-20\if_mult\PrecisionRTL\if_mult_impl_1\rtlc.out\INCR\emptymod.list 设计与验证Verilog HDL\Example-4-20\if_single\PrecisionRTL\if_single_impl_1\rtlc.out\INCR\emptymod.list 设计与验证Verilog HDL\Example-4-20\case\PrecisionRTL\case_impl_1\rtlc.out\INCR\hier.list 设计与验证Verilog HDL\Example-4-20\decode\case\decode_case_impl_1\rtlc.out\INCR\hier.list 设计与验证Verilog HDL\Example-4-20\decode\if_mult\precision_impl_1\rtlc.out\INCR\hier.list 设计与验证Verilog HDL\Example-4-20\decode\if_single\precision_impl_1\rtlc.out\INCR\hier.list 设计与验证Verilog HDL\Example-4-20\if_mult\PrecisionRTL\if_mult_impl_1\rtlc.out\INCR\hier.list 设计与验证Verilog HDL\Example-4-20\if_single\PrecisionRTL\if_single_impl_1\rtlc.out\INCR\hier.list 设计与验证Verilog HDL\Example-4-20\case\PrecisionRTL\case_impl_1\rtlc.out\depend\TOPMODULE.list 设计与验证Verilog HDL\Example-4-20\if_mult\PrecisionRTL\if_mult_impl_1\rtlc.out\depend\TOPMODULE.list 设计与验证Verilog HDL\Example-4-20\if_single\PrecisionRTL\if_single_impl_1\rtlc.out\depend\TOPMODULE.list 设计与验证Verilog HDL\Example-4-20\decode\case\decode_case_impl_1\rtlc.out\depend\TOPMODULE.list 设计与验证Verilog HDL\Example-4-20\decode\if_mult\precision_impl_1\rtlc.out\depend\TOPMODULE.list 设计与验证Verilog HDL\Example-4-20\decode\if_single\precision_impl_1\rtlc.out\depend\TOPMODULE.list 设计与验证Verilog HDL\Example-4-20\case\PrecisionRTL\case_impl_1\rtlc.out\vmw.mem_contents 设计与验证Verilog HDL\Example-4-20\decode\case\decode_case_impl_1\rtlc.out\vmw.mem_contents 设计与验证Verilog HDL\Example-4-20\decode\if_mult\precision_impl_1\rtlc.out\vmw.mem_contents 设计与验证Verilog HDL\Example-4-20\decode\if_single\precision_impl_1\rtlc.out\vmw.mem_contents 设计与验证Verilog HDL\Example-4-20\if_mult\PrecisionRTL\if_mult_impl_1\rtlc.out\vmw.mem_contents 设计与验证Verilog HDL\Example-4-20\if_single\PrecisionRTL\if_single_impl_1\rtlc.out\vmw.mem_contents 设计与验证Verilog HDL\Example-4-20\decode\case\decode_case_impl_1\rtlc_libs\work\case_decode.mod 设计与验证Verilog HDL\Example-4-20\case\PrecisionRTL\case_impl_1\rtlc_libs\work\case1.mod 设计与验证Verilog HDL\Example-4-20\decode\if_mult\precision_impl_1\rtlc_libs\work\if_mult_decode.mod 设计与验证Verilog HDL\Example-4-20\decode\if_single\precision_impl_1\rtlc_libs\work\if_single_decode.mod 设计与验证Verilog HDL\Example-4-20\if_mult\PrecisionRTL\if_mult_impl_1\rtlc_libs\work\mult_if.mod 设计与验证Verilog HDL\Example-4-20\if_single\PrecisionRTL\if_single_impl_1\rtlc_libs\work\single_if.mod 设计与验证Verilog HDL\Example-4-14\clk_div_phase\sim\clk_div.mpf 设计与验证Verilog HDL\Example-4-14\clk_3div\sim\clk_div3.mpf 设计与验证Verilog HDL\Example-4-8\sim\decode_cmb.mpf 设计与验证Verilog HDL\Example-4-13\sim\ram_basic.mpf 设计与验证Verilog HDL\Example-4-7\sim\sim_clock_edge.mpf 设计与验证Verilog HDL\Example-4-17\asyn_rst\rev_1\syntmp\asyn_rst.msg 设计与验证Verilog HDL\Example-4-10\bibus\rev_1\syntmp\bibus.msg 设计与验证Verilog HDL\Example-4-20\decode\case\rev_1\syntmp\case_decode.msg 设计与验证Verilog HDL\Example-4-20\case\SynplifyPro\rev_2\syntmp\case1.msg 设计与验证Verilog HDL\Example-4-14\clk_3div\synthesis\rev_1\syntmp\clk_3div.msg 设计与验证Verilog HDL\Example-4-14\clk_div_phase\rev_1\syntmp\clk_div_phase.msg 设计与验证Verilog HDL\Example-4-7\rev_2\syntmp\clock_edge.msg 设计与验证Verilog HDL\Example-4-1\rev_1\syntmp\cnt2.msg 设计与验证Verilog HDL\Example-4-1\rev_1\syntmp\cnt3.msg 设计与验证Verilog HDL\Example-4-10\complex_bibus\rev_1\syntmp\complex_bibus.msg 设计与验证Verilog HDL\Example-4-21\asyn_bad\rev_1\syntmp\decode.msg 设计与验证Verilog HDL\Example-4-8\rev_2\syntmp\decode_cmb2.msg 设计与验证Verilog HDL\Example-4-20\decode\if_mult\rev_2\syntmp\if_mult_decode.msg 设计与验证Verilog HDL\Example-4-20\decode\if_single\rev_1\syntmp\if_single_decode.msg 设计与验证Verilog HDL\Example-5-5\rev_2\syntmp\latch.msg 设计与验证Verilog HDL\Example-4-20\if_mult\Latch_if_mult\rev_2\syntmp\latch_mult_if.msg 设计与验证Verilog HDL\Example-5-7\rev_1\syntmp\mod_copy1.msg 设计与验证Verilog HDL\Example-4-20\if_mult\SynplifyPro\rev_1\syntmp\mult_if.msg 设计与验证Verilog HDL\Example-4-11\rev_1\syntmp\mux2.msg 设计与验证Verilog HDL\Example-5-7\rev_1\syntmp\proj.msg 设计与验证Verilog HDL\Example-4-13\ram_basic\rev_2\syntmp\ram_basic.msg 设计与验证Verilog HDL\Example-4-4\rev_2\syntmp\reg_counter.msg 设计与验证Verilog HDL\Example-5-6\rev_1\syntmp\resource_share1.msg 设计与验证Verilog HDL\Example-4-20\if_single\SynplifyPro\rev_2\syntmp\single_if.msg 设计与验证Verilog HDL\Example-4-16\rev_1\syntmp\srl2pal.msg 设计与验证Verilog HDL\Example-6-1\FSM\state1\rev_1\syntmp\state1.msg 设计与验证Verilog HDL\Example-6-1\FSM\state2\rev_1\syntmp\state2.msg 设计与验证Verilog HDL\Example-6-1\FSM\state3\rev_2\syntmp\state3.msg 设计与验证Verilog HDL\Example-4-17\syn_rst\rev_2\syntmp\syn_rst.msg 设计与验证Verilog HDL\Example-4-1\source\syntmp.msg 设计与验证Verilog HDL\Example-4-10\bibus\syntmp.msg 设计与验证Verilog HDL\Example-4-10\complex_bibus\syntmp.msg 设计与验证Verilog HDL\Example-4-11\syntmp.msg 设计与验证Verilog HDL\Example-4-17\syn_rst\syntmp.msg 设计与验证Verilog HDL\Example-4-20\case\syntmp.msg 设计与验证Verilog HDL\Example-4-20\if_mult\SynplifyPro\syntmp.msg 设计与验证Verilog HDL\Example-4-20\if_single\SynplifyPro\syntmp.msg 设计与验证Verilog HDL\Example-4-21\syn_wr\syntmp.msg 设计与验证Verilog HDL\Example-4-7\syntmp.msg 设计与验证Verilog HDL\Example-5-5\syntmp.msg 设计与验证Verilog HDL\Example-5-6\source\syntmp.msg 设计与验证Verilog HDL\Example-5-7\source\syntmp.msg 设计与验证Verilog HDL\Example-5-8\source\syntmp.msg 设计与验证Verilog HDL\Example-6-1\FSM\state1\syntmp.msg 设计与验证Verilog HDL\Example-6-1\FSM\state2\syntmp.msg 设计与验证Verilog HDL\Example-4-21\oe_edge\rev_2\syntmp\top.msg 设计与验证Verilog HDL\Example-4-21\syn_wr\rev_1\syntmp\top.msg 设计与验证Verilog HDL\Example-5-8\rev_2\syntmp\un_shannon.msg 设计与验证Verilog HDL\Example-4-14\clk_div_phase\sim\clk_div.cr.mti 设计与验证Verilog HDL\Example-4-14\clk_3div\sim\clk_div3.cr.mti 设计与验证Verilog HDL\Example-4-8\sim\decode_cmb.cr.mti 设计与验证Verilog HDL\Example-4-13\sim\ram_basic.cr.mti 设计与验证Verilog HDL\Example-4-7\sim\sim_clock_edge.cr.mti 设计与验证Verilog HDL\Example-4-14\clk_div_phase\rev_1\clk_div_phase.ncf 设计与验证Verilog HDL\Example-5-5\rev_2\latch.ncf 设计与验证Verilog HDL\Example-4-11\rev_1\mux.ncf 设计与验证Verilog HDL\Example-4-11\rev_1\mux2.ncf 设计与验证Verilog HDL\Example-4-13\ram_basic\rev_2\ram_basic.ncf 设计与验证Verilog HDL\Example-4-4\rev_2\reg_counter.ncf 设计与验证Verilog HDL\Example-4-16\rev_1\srl2pal.ncf 设计与验证Verilog HDL\Example-4-17\asyn_rst\rev_1\syntmp\asyn_rst.plg 设计与验证Verilog HDL\Example-4-10\bibus\rev_1\syntmp\bibus.plg 设计与验证Verilog HDL\Example-4-20\decode\case\rev_1\syntmp\case_decode.plg 设计与验证Verilog HDL\Example-4-20\case\SynplifyPro\rev_2\syntmp\case1.plg 设计与验证Verilog HDL\Example-4-14\clk_3div\synthesis\rev_1\syntmp\clk_3div.plg 设计与验证Verilog HDL\Example-4-14\clk_div_phase\rev_1\syntmp\clk_div_phase.plg 设计与验证Verilog HDL\Example-4-7\rev_2\syntmp\clock_edge.plg 设计与验证Verilog HDL\Example-4-1\rev_1\syntmp\cnt1.plg 设计与验证Verilog HDL\Example-4-1\rev_1\syntmp\cnt2.plg 设计与验证Verilog HDL\Example-4-1\rev_1\syntmp\cnt3.plg 设计与验证Verilog HDL\Example-4-10\complex_bibus\rev_1\syntmp\complex_bibus.plg 设计与验证Verilog HDL\Example-4-10\complex_bibus\rev_1\syntmp\complex_bibus2.plg 设计与验证Verilog HDL\Example-4-21\asyn_bad\rev_1\syntmp\decode.plg 设计与验证Verilog HDL\Example-4-8\rev_2\syntmp\decode_cmb.plg 设计与验证Verilog HDL\Example-4-8\rev_2\syntmp\decode_cmb2.plg 设计与验证Verilog HDL\Example-5-1\before_optimized\rev_1\syntmp\fhtpart.plg 设计与验证Verilog HDL\Example-4-20\decode\if_mult\rev_2\syntmp\if_mult_decode.plg 设计与验证Verilog HDL\Example-4-20\decode\if_single\rev_1\syntmp\if_single_decode.plg 设计与验证Verilog HDL\Example-5-5\rev_2\syntmp\latch.plg 设计与验证Verilog HDL\Example-4-20\if_mult\Latch_if_mult\rev_2\syntmp\latch_mult_if.plg 设计与验证Verilog HDL\Example-5-7\rev_1\syntmp\mod_copy1.plg 设计与验证Verilog HDL\Example-5-7\rev_1\syntmp\mod_copy2.plg 设计与验证Verilog HDL\Example-4-20\if_mult\SynplifyPro\rev_1\syntmp\mult_if.plg 设计与验证Verilog HDL\Example-4-11\rev_1\syntmp\mux.plg 设计与验证Verilog HDL\Example-4-11\rev_1\syntmp\mux2.plg 设计与验证Verilog HDL\Example-4-13\ram_basic\rev_2\syntmp\ram_basic.plg 设计与验证Verilog HDL\Example-4-4\rev_2\syntmp\reg_counter.plg 设计与验证Verilog HDL\Example-5-6\rev_1\syntmp\resource_share1.plg 设计与验证Verilog HDL\Example-5-6\rev_1\syntmp\resource_share2.plg 设计与验证Verilog HDL\Example-5-8\rev_2\syntmp\shannon_fast.plg 设计与验证Verilog HDL\Example-4-20\if_single\SynplifyPro\rev_2\syntmp\single_if.plg 设计与验证Verilog HDL\Example-4-16\rev_1\syntmp\srl2pal.plg 设计与验证Verilog HDL\Example-6-1\FSM\state1\rev_1\syntmp\state1.plg 设计与验证Verilog HDL\Example-6-1\FSM\state2\rev_1\syntmp\state2.plg 设计与验证Verilog HDL\Example-6-1\FSM\state_default\rev_2\syntmp\state2_default.plg 设计与验证Verilog HDL\Example-6-1\FSM\state3\rev_2\syntmp\state3.plg 设计与验证Verilog HDL\Example-4-17\syn_rst\rev_2\syntmp\syn_rst.plg 设计与验证Verilog HDL\Example-4-21\oe_edge\rev_2\syntmp\top.plg 设计与验证Verilog HDL\Example-4-21\syn_wr\rev_1\syntmp\top.plg 设计与验证Verilog HDL\Example-5-8\rev_2\syntmp\un_shannon.plg 设计与验证Verilog HDL\Example-5-1\after_optimized\rev_2\syntmp\wch_fht.plg 设计与验证Verilog HDL\Example-5-1\after_optimized\after_optimized.prd 设计与验证Verilog HDL\Example-4-21\asyn_bad\asyn_bad.prd 设计与验证Verilog HDL\Example-4-17\asyn_rst\asyn_rst.prd 设计与验证Verilog HDL\Example-5-1\before_optimized\before_optimized.prd 设计与验证Verilog HDL\Example-4-10\bibus\bibus.prd 设计与验证Verilog HDL\Example-4-20\case\SynplifyPro\case1.prd 设计与验证Verilog HDL\Example-4-14\clk_div_phase\clk_div_phase.prd 设计与验证Verilog HDL\Example-4-14\clk_3div\synthesis\clk_div3.prd 设计与验证Verilog HDL\Example-4-7\clock_edge.prd 设计与验证Verilog HDL\Example-4-1\cnt.prd 设计与验证Verilog HDL\Example-4-10\complex_bibus\complex_bibus.prd 设计与验证Verilog HDL\Example-4-8\decode_cmb.prd 设计与验证Verilog HDL\Example-4-20\if_mult\SynplifyPro\if_mult.prd 设计与验证Verilog HDL\Example-4-20\decode\if_mult\if_mult_decode.prd 设计与验证Verilog HDL\Example-4-20\if_single\SynplifyPro\if_single.prd 设计与验证Verilog HDL\Example-4-20\decode\if_single\if_single_decode.prd 设计与验证Verilog HDL\Example-5-5\latch.prd 设计与验证Verilog HDL\Example-4-20\if_mult\Latch_if_mult\latch_if_mult.prd 设计与验证Verilog HDL\Example-5-7\mod_copy.prd 设计与验证Verilog HDL\Example-4-11\mux.prd 设计与验证Verilog HDL\Example-4-21\oe_edge\oe_edge.prd 设计与验证Verilog HDL\Example-4-13\ram_basic\ram_basic.prd 设计与验证Verilog HDL\Example-4-4\reg_counter.prd 设计与验证Verilog HDL\Example-5-6\resource_share.prd 设计与验证Verilog HDL\Example-5-8\shannon.prd 设计与验证Verilog HDL\Example-4-16\srl2pal.prd 设计与验证Verilog HDL\Example-6-1\FSM\state_default\state_default.prd 设计与验证Verilog HDL\Example-6-1\FSM\state1\state1.prd 设计与验证Verilog HDL\Example-6-1\FSM\state2\state2.prd 设计与验证Verilog HDL\Example-6-1\FSM\state3\state3.prd 设计与验证Verilog HDL\Example-4-17\syn_rst\syn_rst.prd 设计与验证Verilog HDL\Example-4-21\syn_wr\syn_wr.prd 设计与验证Verilog HDL\Example-4-20\decode\case\synplify.prd 设计与验证Verilog HDL\Example-5-1\workspace_VS.prd 设计与验证Verilog HDL\Example-4-17\asyn_rst\rev_1\asyn_rst.prf 设计与验证Verilog HDL\Example-4-20\decode\case\decode_case_impl_1\case_decode.prf 设计与验证Verilog HDL\Example-4-20\decode\case\rev_1\case_decode.prf 设计与验证Verilog HDL\Example-4-20\case\PrecisionRTL\case_impl_1\case1.prf 设计与验证Verilog HDL\Example-4-20\case\SynplifyPro\rev_2\case1.prf 设计与验证Verilog HDL\Example-4-7\rev_2\clock_edge.prf 设计与验证Verilog HDL\Example-4-21\asyn_bad\rev_1\decode.prf 设计与验证Verilog HDL\Example-4-8\rev_2\decode_cmb.prf 设计与验证Verilog HDL\Example-4-8\rev_2\decode_cmb2.prf 设计与验证Verilog HDL\Example-4-20\decode\if_mult\precision_impl_1\if_mult_decode.prf 设计与验证Verilog HDL\Example-4-20\decode\if_mult\rev_2\if_mult_decode.prf 设计与验证Verilog HDL\Example-4-20\decode\if_single\precision_impl_1\if_single_decode.prf 设计与验证Verilog HDL\Example-4-20\decode\if_single\rev_1\if_single_decode.prf 设计与验证Verilog HDL\Example-4-20\if_mult\Latch_if_mult\rev_2\latch_mult_if.prf 设计与验证Verilog HDL\Example-5-7\rev_1\mod_copy1.prf 设计与验证Verilog HDL\Example-5-7\rev_1\mod_copy2.prf 设计与验证Verilog HDL\Example-4-20\if_mult\PrecisionRTL\if_mult_impl_1\mult_if.prf 设计与验证Verilog HDL\Example-4-20\if_mult\SynplifyPro\rev_1\mult_if.prf 设计与验证Verilog HDL\Example-4-11\rev_1\mux.prf 设计与验证Verilog HDL\Example-4-20\if_single\PrecisionRTL\if_single_impl_1\single_if.prf 设计与验证Verilog HDL\Example-4-20\if_single\SynplifyPro\rev_2\single_if.prf 设计与验证Verilog HDL\Example-6-1\FSM\state1\rev_1\state1.prf 设计与验证Verilog HDL\Example-6-1\FSM\state2\rev_1\state2.prf 设计与验证Verilog HDL\Example-6-1\FSM\state_default\rev_2\state2_default.prf 设计与验证Verilog HDL\Example-6-1\FSM\state3\rev_2\state3.prf 设计与验证Verilog HDL\Example-4-17\syn_rst\rev_2\syn_rst.prf 设计与验证Verilog HDL\Example-4-21\oe_edge\rev_2\top.prf 设计与验证Verilog HDL\Example-4-21\syn_wr\rev_1\top.prf 设计与验证Verilog HDL\Example-5-1\after_optimized\after_optimized.prj 设计与验证Verilog HDL\Example-4-21\asyn_bad\asyn_bad.prj 设计与验证Verilog HDL\Example-4-17\asyn_rst\asyn_rst.prj 设计与验证Verilog HDL\Example-5-1\before_optimized\before_optimized.prj 设计与验证Verilog HDL\Example-4-10\bibus\bibus.prj 设计与验证Verilog HDL\Example-4-20\case\SynplifyPro\case1.prj 设计与验证Verilog HDL\Example-4-14\clk_div_phase\clk_div_phase.prj 设计与验证Verilog HDL\Example-4-14\clk_3div\synthesis\clk_div3.prj 设计与验证Verilog HDL\Example-4-7\clock_edge.prj 设计与验证Verilog HDL\Example-4-1\cnt.prj 设计与验证Verilog HDL\Example-4-10\complex_bibus\complex_bibus.prj 设计与验证Verilog HDL\Example-4-8\decode_cmb.prj 设计与验证Verilog HDL\Example-4-20\if_mult\SynplifyPro\if_mult.prj 设计与验证Verilog HDL\Example-4-20\decode\if_mult\if_mult_decode.prj 设计与验证Verilog HDL\Example-4-20\if_single\SynplifyPro\if_single.prj 设计与验证Verilog HDL\Example-4-20\decode\if_single\if_single_decode.prj 设计与验证Verilog HDL\Example-5-5\latch.prj 设计与验证Verilog HDL\Example-4-20\if_mult\Latch_if_mult\latch_if_mult.prj 设计与验证Verilog HDL\Example-5-7\mod_copy.prj 设计与验证Verilog HDL\Example-4-11\mux.prj 设计与验证Verilog HDL\Example-4-21\oe_edge\oe_edge.prj 设计与验证Verilog HDL\Example-4-13\ram_basic\ram_basic.prj 设计与验证Verilog HDL\Example-4-4\reg_counter.prj 设计与验证Verilog HDL\Example-5-6\resource_share.prj 设计与验证Verilog HDL\Example-5-8\shannon.prj 设计与验证Verilog HDL\Example-4-16\srl2pal.prj 设计与验证Verilog HDL\Example-6-1\FSM\state_default\state_default.prj 设计与验证Verilog HDL\Example-6-1\FSM\state1\state1.prj 设计与验证Verilog HDL\Example-6-1\FSM\state2\state2.prj 设计与验证Verilog HDL\Example-6-1\FSM\state3\state3.prj 设计与验证Verilog HDL\Example-4-17\syn_rst\syn_rst.prj 设计与验证Verilog HDL\Example-4-21\syn_wr\syn_wr.prj 设计与验证Verilog HDL\Example-4-20\decode\case\synplify.prj 设计与验证Verilog HDL\Example-5-1\workspace_VS.prj 设计与验证Verilog HDL\Example-4-20\case\PrecisionRTL\case_impl_1\case_impl_1.psi 设计与验证Verilog HDL\Example-4-20\decode\case\decode_case_impl_1\decode_case_impl_1.psi 设计与验证Verilog HDL\Example-4-20\if_mult\PrecisionRTL\if_mult_impl_1\if_mult_impl_1.psi 设计与验证Verilog HDL\Example-4-20\if_single\PrecisionRTL\if_single_impl_1\if_single_impl_1.psi 设计与验证Verilog HDL\Example-4-20\decode\if_mult\precision_impl_1\precision_impl_1.psi 设计与验证Verilog HDL\Example-4-20\decode\if_single\precision_impl_1\precision_impl_1.psi 设计与验证Verilog HDL\Example-4-20\case\PrecisionRTL\case.psp 设计与验证Verilog HDL\Example-4-20\decode\case\decode_case.psp 设计与验证Verilog HDL\Example-4-20\if_mult\PrecisionRTL\if_mult.psp 设计与验证Verilog HDL\Example-4-20\if_single\PrecisionRTL\if_single.psp 设计与验证Verilog HDL\Example-4-20\decode\if_mult\precision.psp 设计与验证Verilog HDL\Example-4-20\decode\if_single\precision.psp 设计与验证Verilog HDL\Example-4-13\ram_basic\rev_2\.recordref 设计与验证Verilog HDL\Example-4-20\decode\case\decode_case_impl_1\case_decode_area.rep 设计与验证Verilog HDL\Example-4-20\decode\case\decode_case_impl_1\case_decode_timing.rep 设计与验证Verilog HDL\Example-4-20\case\PrecisionRTL\case_impl_1\case1_area.rep 设计与验证Verilog HDL\Example-4-20\case\PrecisionRTL\case_impl_1\case1_timing.rep 设计与验证Verilog HDL\Example-4-20\decode\if_mult\precision_impl_1\if_mult_decode_area.rep 设计与验证Verilog HDL\Example-4-20\decode\if_mult\precision_impl_1\if_mult_decode_timing.rep 设计与验证Verilog HDL\Example-4-20\decode\if_single\precision_impl_1\if_single_decode_area.rep 设计与验证Verilog HDL\Example-4-20\decode\if_single\precision_impl_1\if_single_decode_timing.rep 设计与验证Verilog HDL\Example-4-20\if_mult\PrecisionRTL\if_mult_impl_1\mult_if_area.rep 设计与验证Verilog HDL\Example-4-20\if_mult\PrecisionRTL\if_mult_impl_1\mult_if_timing.rep 设计与验证Verilog HDL\Example-4-20\if_single\PrecisionRTL\if_single_impl_1\single_if_area.rep 设计与验证Verilog HDL\Example-4-20\if_single\PrecisionRTL\if_single_impl_1\single_if_timing.rep 设计与验证Verilog HDL\Example-4-20\case\PrecisionRTL\case_impl_1\rtlc.out\.rtlc_compile 设计与验证Verilog HDL\Example-4-20\decode\case\decode_case_impl_1\rtlc.out\.rtlc_compile 设计与验证Verilog HDL\Example-4-20\decode\if_mult\precision_impl_1\rtlc.out\.rtlc_compile 设计与验证Verilog HDL\Example-4-20\decode\if_single\precision_impl_1\rtlc.out\.rtlc_compile 设计与验证Verilog HDL\Example-4-20\if_mult\PrecisionRTL\if_mult_impl_1\rtlc.out\.rtlc_compile 设计与验证Verilog HDL\Example-4-20\if_single\PrecisionRTL\if_single_impl_1\rtlc.out\.rtlc_compile 设计与验证Verilog HDL\Example-4-17\asyn_rst\rev_1\AutoConstraint_asyn_rst.sdc 设计与验证Verilog HDL\Example-4-20\decode\case\rev_1\AutoConstraint_case_decode.sdc 设计与验证Verilog HDL\Example-4-20\case\SynplifyPro\rev_2\AutoConstraint_case1.sdc 设计与验证Verilog HDL\Example-4-14\clk_div_phase\rev_1\AutoConstraint_clk_div_phase.sdc 设计与验证Verilog HDL\Example-4-10\complex_bibus\rev_1\AutoConstraint_complex_bibus.sdc 设计与验证Verilog HDL\Example-5-1\before_optimized\rev_1\AutoConstraint_fhtpart.sdc 设计与验证Verilog HDL\Example-4-20\decode\if_mult\rev_2\AutoConstraint_if_mult_decode.sdc 设计与验证Verilog HDL\Example-4-20\decode\if_single\rev_1\AutoConstraint_if_single_decode.sdc 设计与验证Verilog HDL\Example-5-5\rev_2\AutoConstraint_latch.sdc 设计与验证Verilog HDL\Example-5-7\rev_1\AutoConstraint_mod_copy1.sdc 设计与验证Verilog HDL\Example-4-20\if_mult\Latch_if_mult\rev_2\AutoConstraint_mult_if.sdc 设计与验证Verilog HDL\Example-4-20\if_mult\SynplifyPro\rev_1\AutoConstraint_mult_if.sdc 设计与验证Verilog HDL\Example-4-11\rev_1\AutoConstraint_mux.sdc 设计与验证Verilog HDL\Example-4-13\ram_basic\rev_2\AutoConstraint_ram_basic.sdc 设计与验证Verilog HDL\Example-5-6\rev_1\AutoConstraint_resource_share1.sdc 设计与验证Verilog HDL\Example-5-6\rev_1\AutoConstraint_resource_share2.sdc 设计与验证Verilog HDL\Example-5-8\rev_2\AutoConstraint_shannon_fast.sdc 设计与验证Verilog HDL\Example-4-20\if_single\SynplifyPro\rev_2\AutoConstraint_single_if.sdc 设计与验证Verilog HDL\Example-4-16\rev_1\AutoConstraint_srl2pal.sdc 设计与验证Verilog HDL\Example-6-1\FSM\state1\rev_1\AutoConstraint_state1.sdc 设计与验证Verilog HDL\Example-6-1\FSM\state2\rev_1\AutoConstraint_state2.sdc 设计与验证Verilog HDL\Example-6-1\FSM\state3\rev_2\AutoConstraint_state2.sdc 设计与验证Verilog HDL\Example-6-1\FSM\state_default\rev_2\AutoConstraint_state2_default.sdc 设计与验证Verilog HDL\Example-4-17\syn_rst\rev_2\AutoConstraint_syn_rst.sdc 设计与验证Verilog HDL\Example-4-21\asyn_bad\rev_1\AutoConstraint_top.sdc 设计与验证Verilog HDL\Example-4-21\oe_edge\rev_2\AutoConstraint_top.sdc 设计与验证Verilog HDL\Example-5-8\rev_2\AutoConstraint_un_shannon.sdc 设计与验证Verilog HDL\Example-4-20\decode\case\decode_case_impl_1\case_decode_con_rep.sdc 设计与验证Verilog HDL\Example-4-20\decode\case\decode_case_impl_1\case_decode_tech_con_rep.sdc 设计与验证Verilog HDL\Example-4-20\case\PrecisionRTL\case_impl_1\case1_con_rep.sdc 设计与验证Verilog HDL\Example-4-20\case\PrecisionRTL\case_impl_1\case1_tech_con_rep.sdc 设计与验证Verilog HDL\Example-4-20\decode\if_mult\precision_impl_1\if_mult_decode_con_rep.sdc 设计与验证Verilog HDL\Example-4-20\decode\if_mult\precision_impl_1\if_mult_decode_tech_con_rep.sdc 设计与验证Verilog HDL\Example-4-20\decode\if_single\precision_impl_1\if_single_decode_con_rep.sdc 设计与验证Verilog HDL\Example-4-20\decode\if_single\precision_impl_1\if_single_decode_tech_con_rep.sdc 设计与验证Verilog HDL\Example-4-20\if_mult\PrecisionRTL\if_mult_impl_1\mult_if_con_rep.sdc 设计与验证Verilog HDL\Example-4-20\if_mult\PrecisionRTL\if_mult_impl_1\mult_if_tech_con_rep.sdc 设计与验证Verilog HDL\Example-4-20\case\PrecisionRTL\case_impl_1\precision_rtl.sdc 设计与验证Verilog HDL\Example-4-20\decode\case\decode_case_impl_1\precision_rtl.sdc 设计与验证Verilog HDL\Example-4-20\decode\if_mult\precision_impl_1\precision_rtl.sdc 设计与验证Verilog HDL\Example-4-20\decode\if_single\precision_impl_1\precision_rtl.sdc 设计与验证Verilog HDL\Example-4-20\if_mult\PrecisionRTL\if_mult_impl_1\precision_rtl.sdc 设计与验证Verilog HDL\Example-4-20\if_single\PrecisionRTL\if_single_impl_1\precision_rtl.sdc 设计与验证Verilog HDL\Example-4-20\case\PrecisionRTL\case_impl_1\precision_tech.sdc 设计与验证Verilog HDL\Example-4-20\decode\case\decode_case_impl_1\precision_tech.sdc 设计与验证Verilog HDL\Example-4-20\decode\if_mult\precision_impl_1\precision_tech.sdc 设计与验证Verilog HDL\Example-4-20\decode\if_single\precision_impl_1\precision_tech.sdc 设计与验证Verilog HDL\Example-4-20\if_mult\PrecisionRTL\if_mult_impl_1\precision_tech.sdc 设计与验证Verilog HDL\Example-4-20\if_single\PrecisionRTL\if_single_impl_1\precision_tech.sdc 设计与验证Verilog HDL\Example-4-20\if_single\PrecisionRTL\if_single_impl_1\single_if_con_rep.sdc 设计与验证Verilog HDL\Example-4-20\if_single\PrecisionRTL\if_single_impl_1\single_if_tech_con_rep.sdc 设计与验证Verilog HDL\Example-6-1\FSM\state2\rev_1\state2_fsm.sdc 设计与验证Verilog HDL\Example-4-10\bibus\rev_1\bibus.srd 设计与验证Verilog HDL\Example-4-14\clk_div_phase\rev_1\clk_div_phase.srd 设计与验证Verilog HDL\Example-4-10\complex_bibus\rev_1\complex_bibus.srd 设计与验证Verilog HDL\Example-4-10\complex_bibus\rev_1\complex_bibus2.srd 设计与验证Verilog HDL\Example-5-1\before_optimized\rev_1\fhtpart.srd 设计与验证Verilog HDL\Example-5-7\rev_1\generic.srd 设计与验证Verilog HDL\Example-4-11\rev_1\generic.srd 设计与验证Verilog HDL\Example-4-20\decode\case\rev_1\generic.srd 设计与验证Verilog HDL\Example-4-20\decode\if_single\rev_1\generic.srd 设计与验证Verilog HDL\Example-4-20\decode\if_mult\rev_2\generic.srd 设计与验证Verilog HDL\Example-4-8\rev_2\generic.srd 设计与验证Verilog HDL\Example-4-20\case\SynplifyPro\rev_2\generic.srd 设计与验证Verilog HDL\Example-4-20\if_single\SynplifyPro\rev_2\generic.srd 设计与验证Verilog HDL\Example-4-20\if_mult\SynplifyPro\rev_1\generic.srd 设计与验证Verilog HDL\Example-4-20\if_mult\Latch_if_mult\rev_2\generic.srd 设计与验证Verilog HDL\Example-6-1\FSM\state2\rev_1\generic.srd 设计与验证Verilog HDL\Example-6-1\FSM\state_default\rev_2\generic.srd 设计与验证Verilog HDL\Example-6-1\FSM\state3\rev_2\generic.srd 设计与验证Verilog HDL\Example-6-1\FSM\state1\rev_1\generic.srd 设计与验证Verilog HDL\Example-4-17\asyn_rst\rev_1\generic.srd 设计与验证Verilog HDL\Example-4-17\syn_rst\rev_2\generic.srd 设计与验证Verilog HDL\Example-4-7\rev_2\generic.srd 设计与验证Verilog HDL\Example-4-21\asyn_bad\rev_1\generic.srd 设计与验证Verilog HDL\Example-4-21\oe_edge\rev_2\generic.srd 设计与验证Verilog HDL\Example-4-21\syn_wr\rev_1\generic.srd 设计与验证Verilog HDL\Example-5-5\rev_2\latch.srd 设计与验证Verilog HDL\Example-4-11\rev_1\mux.srd 设计与验证Verilog HDL\Example-4-11\rev_1\mux2.srd 设计与验证Verilog HDL\Example-4-13\ram_basic\rev_2\ram_basic.srd 设计与验证Verilog HDL\Example-4-4\rev_2\reg_counter.srd 设计与验证Verilog HDL\Example-5-6\rev_1\resource_share1.srd 设计与验证Verilog HDL\Example-5-6\rev_1\resource_share2.srd 设计与验证Verilog HDL\Example-5-8\rev_2\shannon_fast.srd 设计与验证Verilog HDL\Example-4-16\rev_1\srl2pal.srd 设计与验证Verilog HDL\Example-6-1\FSM\state2\rev_1\state2.srd 设计与验证Verilog HDL\Example-5-8\rev_2\un_shannon.srd 设计与验证Verilog HDL\Example-5-1\after_optimized\rev_2\wch_fht.srd 设计与验证Verilog HDL\Example-4-17\asyn_rst\rev_1\asyn_rst.srm 设计与验证Verilog HDL\Example-4-10\bibus\rev_1\bibus.srm 设计与验证Verilog HDL\Example-4-20\decode\case\rev_1\case_decode.srm 设计与验证Verilog HDL\Example-4-20\case\SynplifyPro\rev_2\case1.srm 设计与验证Verilog HDL\Example-4-14\clk_3div\synthesis\rev_1\clk_3div.srm 设计与验证Verilog HDL\Example-4-14\clk_div_phase\rev_1\clk_div_phase.srm 设计与验证Verilog HDL\Example-4-7\rev_2\clock_edge.srm 设计与验证Verilog HDL\Example-4-1\rev_1\cnt1.srm 设计与验证Verilog HDL\Example-4-1\rev_1\cnt2.srm 设计与验证Verilog HDL\Example-4-1\rev_1\cnt3.srm 设计与验证Verilog HDL\Example-4-10\complex_bibus\rev_1\complex_bibus.srm 设计与验证Verilog HDL\Example-4-10\complex_bibus\rev_1\complex_bibus2.srm 设计与验证Verilog HDL\Example-4-21\asyn_bad\rev_1\decode.srm 设计与验证Verilog HDL\Example-4-8\rev_2\decode_cmb.srm 设计与验证Verilog HDL\Example-4-8\rev_2\decode_cmb2.srm 设计与验证Verilog HDL\Example-5-1\before_optimized\rev_1\fhtpart.srm 设计与验证Verilog HDL\Example-4-20\decode\if_mult\rev_2\if_mult_decode.srm 设计与验证Verilog HDL\Example-4-20\decode\if_single\rev_1\if_single_decode.srm 设计与验证Verilog HDL\Example-5-5\rev_2\latch.srm 设计与验证Verilog HDL\Example-4-20\if_mult\Latch_if_mult\rev_2\latch_mult_if.srm 设计与验证Verilog HDL\Example-5-7\rev_1\mod_copy1.srm 设计与验证Verilog HDL\Example-5-7\rev_1\mod_copy2.srm 设计与验证Verilog HDL\Example-4-20\if_mult\SynplifyPro\rev_1\mult_if.srm 设计与验证Verilog HDL\Example-4-11\rev_1\mux.srm 设计与验证Verilog HDL\Example-4-11\rev_1\mux2.srm 设计与验证Verilog HDL\Example-4-13\ram_basic\rev_2\ram_basic.srm 设计与验证Verilog HDL\Example-4-4\rev_2\reg_counter.srm 设计与验证Verilog HDL\Example-5-6\rev_1\resource_share1.srm 设计与验证Verilog HDL\Example-5-6\rev_1\resource_share2.srm 设计与验证Verilog HDL\Example-5-8\rev_2\shannon_fast.srm 设计与验证Verilog HDL\Example-4-20\if_single\SynplifyPro\rev_2\single_if.srm 设计与验证Verilog HDL\Example-4-16\rev_1\srl2pal.srm 设计与验证Verilog HDL\Example-6-1\FSM\state1\rev_1\state1.srm 设计与验证Verilog HDL\Example-6-1\FSM\state2\rev_1\state2.srm 设计与验证Verilog HDL\Example-6-1\FSM\state_default\rev_2\state2_default.srm 设计与验证Verilog HDL\Example-6-1\FSM\state3\rev_2\state3.srm 设计与验证Verilog HDL\Example-4-17\syn_rst\rev_2\syn_rst.srm 设计与验证Verilog HDL\Example-4-21\oe_edge\rev_2\top.srm 设计与验证Verilog HDL\Example-4-21\syn_wr\rev_1\top.srm 设计与验证Verilog HDL\Example-5-8\rev_2\un_shannon.srm 设计与验证Verilog HDL\Example-5-1\after_optimized\rev_2\wch_fht.srm 设计与验证Verilog HDL\Example-4-17\asyn_rst\rev_1\asyn_rst.srr 设计与验证Verilog HDL\Example-4-10\bibus\rev_1\bibus.srr 设计与验证Verilog HDL\Example-4-20\decode\case\rev_1\case_decode.srr 设计与验证Verilog HDL\Example-4-20\case\SynplifyPro\rev_2\case1.srr 设计与验证Verilog HDL\Example-4-14\clk_3div\synthesis\rev_1\clk_3div.srr 设计与验证Verilog HDL\Example-4-14\clk_div_phase\rev_1\clk_div_phase.srr 设计与验证Verilog HDL\Example-4-7\rev_2\clock_edge.srr 设计与验证Verilog HDL\Example-4-1\rev_1\cnt1.srr 设计与验证Verilog HDL\Example-4-1\rev_1\cnt2.srr 设计与验证Verilog HDL\Example-4-1\rev_1\cnt3.srr 设计与验证Verilog HDL\Example-4-10\complex_bibus\rev_1\complex_bibus.srr 设计与验证Verilog HDL\Example-4-10\complex_bibus\rev_1\complex_bibus2.srr 设计与验证Verilog HDL\Example-4-10\complex_bibus\rev_1\decode.srr 设计与验证Verilog HDL\Example-4-21\asyn_bad\rev_1\decode.srr 设计与验证Verilog HDL\Example-4-8\rev_2\decode_cmb.srr 设计与验证Verilog HDL\Example-4-8\rev_2\decode_cmb2.srr 设计与验证Verilog HDL\Example-5-1\before_optimized\rev_1\fhtpart.srr 设计与验证Verilog HDL\Example-4-20\decode\if_mult\rev_2\if_mult_decode.srr 设计与验证Verilog HDL\Example-4-20\decode\if_single\rev_1\if_single_decode.srr 设计与验证Verilog HDL\Example-5-5\rev_2\latch.srr 设计与验证Verilog HDL\Example-4-20\if_mult\Latch_if_mult\rev_2\latch_mult_if.srr 设计与验证Verilog HDL\Example-5-7\rev_1\mod_copy1.srr 设计与验证Verilog HDL\Example-5-7\rev_1\mod_copy2.srr 设计与验证Verilog HDL\Example-4-20\if_mult\SynplifyPro\rev_1\mult_if.srr 设计与验证Verilog HDL\Example-4-11\rev_1\mux.srr 设计与验证Verilog HDL\Example-4-11\rev_1\mux2.srr 设计与验证Verilog HDL\Example-4-13\ram_basic\rev_2\ram_basic.srr 设计与验证Verilog HDL\Example-4-4\rev_2\reg_counter.srr 设计与验证Verilog HDL\Example-5-6\rev_1\resource_share1.srr 设计与验证Verilog HDL\Example-5-6\rev_1\resource_share2.srr 设计与验证Verilog HDL\Example-5-8\rev_2\shannon_fast.srr 设计与验证Verilog HDL\Example-4-20\if_single\SynplifyPro\rev_2\single_if.srr 设计与验证Verilog HDL\Example-4-16\rev_1\srl2pal.srr 设计与验证Verilog HDL\Example-6-1\FSM\state1\rev_1\state1.srr 设计与验证Verilog HDL\Example-6-1\FSM\state2\rev_1\state2.srr 设计与验证Verilog HDL\Example-6-1\FSM\state_default\rev_2\state2_default.srr 设计与验证Verilog HDL\Example-6-1\FSM\state3\rev_2\state3.srr 设计与验证Verilog HDL\Example-4-17\syn_rst\rev_2\syn_rst.srr 设计与验证Verilog HDL\Example-4-21\syn_wr\rev_1\top.srr 设计与验证Verilog HDL\Example-4-21\oe_edge\rev_2\top.srr 设计与验证Verilog HDL\Example-5-8\rev_2\un_shannon.srr 设计与验证Verilog HDL\Example-5-1\after_optimized\rev_2\wch_fht.srr 设计与验证Verilog HDL\Example-4-17\asyn_rst\rev_1\asyn_rst.srs 设计与验证Verilog HDL\Example-4-10\bibus\rev_1\bibus.srs 设计与验证Verilog HDL\Example-4-20\decode\case\rev_1\case_decode.srs 设计与验证Verilog HDL\Example-4-20\case\SynplifyPro\rev_2\case1.srs 设计与验证Verilog HDL\Example-4-14\clk_3div\synthesis\rev_1\clk_3div.srs 设计与验证Verilog HDL\Example-4-14\clk_div_phase\rev_1\clk_div_phase.srs 设计与验证Verilog HDL\Example-4-7\rev_2\clock_edge.srs 设计与验证Verilog HDL\Example-4-1\rev_1\cnt1.srs 设计与验证Verilog HDL\Example-4-1\rev_1\cnt2.srs 设计与验证Verilog HDL\Example-4-1\rev_1\cnt3.srs 设计与验证Verilog HDL\Example-4-10\complex_bibus\rev_1\complex_bibus.srs 设计与验证Verilog HDL\Example-4-10\complex_bibus\rev_1\complex_bibus2.srs 设计与验证Verilog HDL\Example-4-21\asyn_bad\rev_1\decode.srs 设计与验证Verilog HDL\Example-4-8\rev_2\decode_cmb.srs 设计与验证Verilog HDL\Example-4-8\rev_2\decode_cmb2.srs 设计与验证Verilog HDL\Example-5-1\before_optimized\rev_1\fhtpart.srs 设计与验证Verilog HDL\Example-4-20\decode\if_mult\rev_2\if_mult_decode.srs 设计与验证Verilog HDL\Example-4-20\decode\if_single\rev_1\if_single_decode.srs 设计与验证Verilog HDL\Example-5-5\rev_2\latch.srs 设计与验证Verilog HDL\Example-4-20\if_mult\Latch_if_mult\rev_2\latch_mult_if.srs 设计与验证Verilog HDL\Example-5-7\rev_1\mod_copy1.srs 设计与验证Verilog HDL\Example-5-7\rev_1\mod_copy2.srs 设计与验证Verilog HDL\Example-4-20\if_mult\SynplifyPro\rev_1\mult_if.srs 设计与验证Verilog HDL\Example-4-11\rev_1\mux.srs 设计与验证Verilog HDL\Example-4-11\rev_1\mux2.srs 设计与验证Verilog HDL\Example-4-13\ram_basic\rev_2\ram_basic.srs 设计与验证Verilog HDL\Example-4-4\rev_2\reg_counter.srs 设计与验证Verilog HDL\Example-5-6\rev_1\resource_share1.srs 设计与验证Verilog HDL\Example-5-6\rev_1\resource_share2.srs 设计与验证Verilog HDL\Example-5-8\rev_2\shannon_fast.srs 设计与验证Verilog HDL\Example-4-20\if_single\SynplifyPro\rev_2\single_if.srs 设计与验证Verilog HDL\Example-4-16\rev_1\srl2pal.srs 设计与验证Verilog HDL\Example-6-1\FSM\state1\rev_1\state1.srs 设计与验证Verilog HDL\Example-6-1\FSM\state2\rev_1\state2.srs 设计与验证Verilog HDL\Example-6-1\FSM\state_default\rev_2\state2_default.srs 设计与验证Verilog HDL\Example-6-1\FSM\state3\rev_2\state3.srs 设计与验证Verilog HDL\Example-4-17\syn_rst\rev_2\syn_rst.srs 设计与验证Verilog HDL\Example-4-21\oe_edge\rev_2\top.srs 设计与验证Verilog HDL\Example-4-21\syn_wr\rev_1\top.srs 设计与验证Verilog HDL\Example-5-8\rev_2\un_shannon.srs 设计与验证Verilog HDL\Example-5-1\after_optimized\rev_2\wch_fht.srs 设计与验证Verilog HDL\Example-4-10\bibus\rev_1\bibus.sxr 设计与验证Verilog HDL\Example-4-10\complex_bibus\rev_1\complex_bibus.sxr 设计与验证Verilog HDL\Example-4-10\complex_bibus\rev_1\complex_bibus2.sxr 设计与验证Verilog HDL\Example-5-1\before_optimized\rev_1\fhtpart.sxr 设计与验证Verilog HDL\Example-4-11\rev_1\mux.sxr 设计与验证Verilog HDL\Example-5-6\rev_1\resource_share1.sxr 设计与验证Verilog HDL\Example-5-6\rev_1\resource_share2.sxr 设计与验证Verilog HDL\Example-5-8\rev_2\shannon_fast.sxr 设计与验证Verilog HDL\Example-6-1\FSM\state2\rev_1\state2.sxr 设计与验证Verilog HDL\Example-5-8\rev_2\un_shannon.sxr 设计与验证Verilog HDL\Example-5-1\after_optimized\rev_2\wch_fht.sxr 设计与验证Verilog HDL\Example-4-10\bibus\rev_1\bibus.tcl 设计与验证Verilog HDL\Example-4-10\bibus\rev_1\bibus_cons.tcl 设计与验证Verilog HDL\Example-4-10\bibus\rev_1\syntmp\bibus_cons_ui.tcl 设计与验证Verilog HDL\Example-4-10\bibus\rev_1\bibus_rm.tcl 设计与验证Verilog HDL\Example-4-10\complex_bibus\rev_1\complex_bibus.tcl 设计与验证Verilog HDL\Example-4-10\complex_bibus\rev_1\complex_bibus_cons.tcl 设计与验证Verilog HDL\Example-4-10\complex_bibus\rev_1\syntmp\complex_bibus_cons_ui.tcl 设计与验证Verilog HDL\Example-4-10\complex_bibus\rev_1\complex_bibus_rm.tcl 设计与验证Verilog HDL\Example-4-10\complex_bibus\rev_1\complex_bibus2.tcl 设计与验证Verilog HDL\Example-4-10\complex_bibus\rev_1\complex_bibus2_cons.tcl 设计与验证Verilog HDL\Example-4-10\complex_bibus\rev_1\syntmp\complex_bibus2_cons_ui.tcl 设计与验证Verilog HDL\Example-4-10\complex_bibus\rev_1\complex_bibus2_rm.tcl 设计与验证Verilog HDL\Example-5-1\before_optimized\rev_1\fhtpart.tcl 设计与验证Verilog HDL\Example-5-1\before_optimized\rev_1\fhtpart_cons.tcl 设计与验证Verilog HDL\Example-5-1\before_optimized\rev_1\fhtpart_rm.tcl 设计与验证Verilog HDL\Example-6-1\FSM\state2\rev_1\syntmp\fsm_tmp_cons_ui.tcl 设计与验证Verilog HDL\Example-4-11\rev_1\mux.tcl 设计与验证Verilog HDL\Example-4-11\rev_1\mux_cons.tcl 设计与验证Verilog HDL\Example-4-11\rev_1\syntmp\mux_cons_ui.tcl 设计与验证Verilog HDL\Example-4-11\rev_1\mux_rm.tcl 设计与验证Verilog HDL\Example-5-6\rev_1\resource_share1.tcl 设计与验证Verilog HDL\Example-5-6\rev_1\resource_share1_cons.tcl 设计与验证Verilog HDL\Example-5-6\rev_1\syntmp\resource_share1_cons_ui.tcl 设计与验证Verilog HDL\Example-5-6\rev_1\resource_share1_rm.tcl 设计与验证Verilog HDL\Example-5-6\rev_1\resource_share2.tcl 设计与验证Verilog HDL\Example-5-6\rev_1\resource_share2_cons.tcl 设计与验证Verilog HDL\Example-5-6\rev_1\syntmp\resource_share2_cons_ui.tcl 设计与验证Verilog HDL\Example-5-6\rev_1\resource_share2_rm.tcl 设计与验证Verilog HDL\Example-5-8\rev_2\shannon_fast.tcl 设计与验证Verilog HDL\Example-5-8\rev_2\shannon_fast_cons.tcl 设计与验证Verilog HDL\Example-5-8\rev_2\syntmp\shannon_fast_cons_ui.tcl 设计与验证Verilog HDL\Example-5-8\rev_2\shannon_fast_rm.tcl 设计与验证Verilog HDL\Example-6-1\FSM\state2\rev_1\state2.tcl 设计与验证Verilog HDL\Example-6-1\FSM\state2\rev_1\state2_cons.tcl 设计与验证Verilog HDL\Example-6-1\FSM\state2\rev_1\syntmp\state2_cons_ui.tcl 设计与验证Verilog HDL\Example-6-1\FSM\state2\rev_1\state2_rm.tcl 设计与验证Verilog HDL\Example-5-8\rev_2\un_shannon.tcl 设计与验证Verilog HDL\Example-5-8\rev_2\un_shannon_cons.tcl 设计与验证Verilog HDL\Example-5-8\rev_2\syntmp\un_shannon_cons_ui.tcl 设计与验证Verilog HDL\Example-5-8\rev_2\un_shannon_rm.tcl 设计与验证Verilog HDL\Example-5-1\after_optimized\rev_2\wch_fht.tcl 设计与验证Verilog HDL\Example-5-1\after_optimized\rev_2\wch_fht_cons.tcl 设计与验证Verilog HDL\Example-5-1\after_optimized\rev_2\wch_fht_rm.tcl 设计与验证Verilog HDL\Example-4-17\asyn_rst\rev_1\asyn_rst.tlg 设计与验证Verilog HDL\Example-4-10\bibus\rev_1\bibus.tlg 设计与验证Verilog HDL\Example-4-20\decode\case\rev_1\case_decode.tlg 设计与验证Verilog HDL\Example-4-20\case\SynplifyPro\rev_2\case1.tlg 设计与验证Verilog HDL\Example-4-14\clk_3div\synthesis\rev_1\clk_3div.tlg 设计与验证Verilog HDL\Example-4-14\clk_div_phase\rev_1\clk_div_phase.tlg 设计与验证Verilog HDL\Example-4-7\rev_2\clock_edge.tlg 设计与验证Verilog HDL\Example-4-1\rev_1\cnt1.tlg 设计与验证Verilog HDL\Example-4-1\rev_1\cnt2.tlg 设计与验证Verilog HDL\Example-4-1\rev_1\cnt3.tlg 设计与验证Verilog HDL\Example-4-10\complex_bibus\rev_1\complex_bibus.tlg 设计与验证Verilog HDL\Example-4-10\complex_bibus\rev_1\complex_bibus2.tlg 设计与验证Verilog HDL\Example-4-21\asyn_bad\rev_1\decode.tlg 设计与验证Verilog HDL\Example-4-8\rev_2\decode_cmb.tlg 设计与验证Verilog HDL\Example-4-8\rev_2\decode_cmb2.tlg 设计与验证Verilog HDL\Example-5-1\before_optimized\rev_1\fhtpart.tlg 设计与验证Verilog HDL\Example-4-20\decode\if_mult\rev_2\if_mult_decode.tlg 设计与验证Verilog HDL\Example-4-20\decode\if_single\rev_1\if_single_decode.tlg 设计与验证Verilog HDL\Example-5-5\rev_2\latch.tlg 设计与验证Verilog HDL\Example-4-20\if_mult\Latch_if_mult\rev_2\latch_mult_if.tlg 设计与验证Verilog HDL\Example-5-7\rev_1\mod_copy1.tlg 设计与验证Verilog HDL\Example-5-7\rev_1\mod_copy2.tlg 设计与验证Verilog HDL\Example-4-20\if_mult\SynplifyPro\rev_1\mult_if.tlg 设计与验证Verilog HDL\Example-4-11\rev_1\mux.tlg 设计与验证Verilog HDL\Example-4-11\rev_1\mux2.tlg 设计与验证Verilog HDL\Example-4-13\ram_basic\rev_2\ram_basic.tlg 设计与验证Verilog HDL\Example-4-4\rev_2\reg_counter.tlg 设计与验证Verilog HDL\Example-5-6\rev_1\resource_share1.tlg 设计与验证Verilog HDL\Example-5-6\rev_1\resource_share2.tlg 设计与验证Verilog HDL\Example-5-8\rev_2\shannon_fast.tlg 设计与验证Verilog HDL\Example-4-20\if_single\SynplifyPro\rev_2\single_if.tlg 设计与验证Verilog HDL\Example-4-16\rev_1\srl2pal.tlg 设计与验证Verilog HDL\Example-6-1\FSM\state1\rev_1\state1.tlg 设计与验证Verilog HDL\Example-6-1\FSM\state2\rev_1\state2.tlg 设计与验证Verilog HDL\Example-6-1\FSM\state_default\rev_2\state2_default.tlg 设计与验证Verilog HDL\Exa