文件名称:xapp134_vhdl
- 所属分类：
- 其它资源
- 资源属性：
- [ASM] [源码]
- 上传时间：
- 2008-10-13
- 文件大小：
- 2.51mb
- 下载次数：
- 0次
- 提 供 者：
- ronsu******
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The SDRAM controller is designed for the Virtex V300bg432-6. It s simulated
with Micron SDRAM models. The design is verified with timing constraints at
115 MHZ.
with Micron SDRAM models. The design is verified with timing constraints at
115 MHZ.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
压缩包 : 41695069xapp134_vhdl.zip 列表 vhdl/ vhdl/func_sim/ vhdl/func_sim/brst_cntr.vhd vhdl/func_sim/cslt_cntr.vhd vhdl/func_sim/ki_cntr.vhd vhdl/func_sim/load.do vhdl/func_sim/mt48lc1m16a1.v vhdl/func_sim/mti_pkg.vhd vhdl/func_sim/rcd_cntr.vhd vhdl/func_sim/ref_cntr.vhd vhdl/func_sim/run_sim.do vhdl/func_sim/sdrm.vhd vhdl/func_sim/sdrmc_state.vhd vhdl/func_sim/sdrm_t.vhd vhdl/func_sim/state.do vhdl/func_sim/sys_int.vhd vhdl/func_sim/tb_sdrm.v vhdl/func_sim/transcript vhdl/func_sim/verwave.do vhdl/func_sim/work/ vhdl/func_sim/work/brst_cntr/ vhdl/func_sim/work/brst_cntr/brst_cntr_arch.asm vhdl/func_sim/work/brst_cntr/brst_cntr_arch.dat vhdl/func_sim/work/brst_cntr/_primary.dat vhdl/func_sim/work/cslt_cntr/ vhdl/func_sim/work/cslt_cntr/cslt_cntr_arch.asm vhdl/func_sim/work/cslt_cntr/cslt_cntr_arch.dat vhdl/func_sim/work/cslt_cntr/_primary.dat vhdl/func_sim/work/ki_cntr/ vhdl/func_sim/work/ki_cntr/ki_cntr_arch.asm vhdl/func_sim/work/ki_cntr/ki_cntr_arch.dat vhdl/func_sim/work/ki_cntr/_primary.dat vhdl/func_sim/work/mt48lc1m16a1/ vhdl/func_sim/work/mt48lc1m16a1/verilog.asm vhdl/func_sim/work/mt48lc1m16a1/_primary.dat vhdl/func_sim/work/mt48lc1m16a1/_primary.vhd vhdl/func_sim/work/mti_pkg/ vhdl/func_sim/work/mti_pkg/body.asm vhdl/func_sim/work/mti_pkg/body.dat vhdl/func_sim/work/mti_pkg/_primary.dat vhdl/func_sim/work/mti_pkg/_vhdl.asm vhdl/func_sim/work/rcd_cntr/ vhdl/func_sim/work/rcd_cntr/rcd_cntr_arch.asm vhdl/func_sim/work/rcd_cntr/rcd_cntr_arch.dat vhdl/func_sim/work/rcd_cntr/_primary.dat vhdl/func_sim/work/ref_cntr/ vhdl/func_sim/work/ref_cntr/ref_cntr_arch.asm vhdl/func_sim/work/ref_cntr/ref_cntr_arch.dat vhdl/func_sim/work/ref_cntr/_primary.dat vhdl/func_sim/work/sdrm/ vhdl/func_sim/work/sdrm/sdrm_arch.asm vhdl/func_sim/work/sdrm/sdrm_arch.dat vhdl/func_sim/work/sdrm/_primary.dat vhdl/func_sim/work/sdrmc_state/ vhdl/func_sim/work/sdrmc_state/sdrmc_state_arch.asm vhdl/func_sim/work/sdrmc_state/sdrmc_state_arch.dat vhdl/func_sim/work/sdrmc_state/_primary.dat vhdl/func_sim/work/sdrm_t/ vhdl/func_sim/work/sdrm_t/sdrm_t_arch.asm vhdl/func_sim/work/sdrm_t/sdrm_t_arch.dat vhdl/func_sim/work/sdrm_t/_primary.dat vhdl/func_sim/work/sys_int/ vhdl/func_sim/work/sys_int/sys_int_arch.asm vhdl/func_sim/work/sys_int/sys_int_arch.dat vhdl/func_sim/work/sys_int/_primary.dat vhdl/func_sim/work/t_sdrm/ vhdl/func_sim/work/t_sdrm/testbench.asm vhdl/func_sim/work/t_sdrm/testbench.dat vhdl/func_sim/work/t_sdrm/verilog.asm vhdl/func_sim/work/t_sdrm/_primary.dat vhdl/func_sim/work/t_sdrm/_primary.vhd vhdl/func_sim/work/_info vhdl/micron/ vhdl/micron/bank0.txt vhdl/micron/bank1.txt vhdl/micron/mt48lc1m16a1-8a.v vhdl/micron/mt48lc1m16a1.v vhdl/micron/test.v vhdl/par/ vhdl/par/sdrm.bit vhdl/par/sdrm.edf vhdl/par/sdrm.ll vhdl/par/sdrm.ncf vhdl/par/xproj/ vhdl/par/xproj/sdrm.xpj vhdl/par/xproj/ver1/ vhdl/par/xproj/ver1/netlist.lst vhdl/par/xproj/ver1/rev1/ vhdl/par/xproj/ver1/rev1/bitgen.ut vhdl/par/xproj/ver1/rev1/command.his vhdl/par/xproj/ver1/rev1/fe.log vhdl/par/xproj/ver1/rev1/map.mrp vhdl/par/xproj/ver1/rev1/map.ncd vhdl/par/xproj/ver1/rev1/map.ngm vhdl/par/xproj/ver1/rev1/ngd2ver.log vhdl/par/xproj/ver1/rev1/ngd2vhdl.log vhdl/par/xproj/ver1/rev1/program.his vhdl/par/xproj/ver1/rev1/revision.obf vhdl/par/xproj/ver1/rev1/revision.rbf vhdl/par/xproj/ver1/rev1/rptbrwsr.dat vhdl/par/xproj/ver1/rev1/sdrm.alf vhdl/par/xproj/ver1/rev1/sdrm.bgn vhdl/par/xproj/ver1/rev1/sdrm.bit vhdl/par/xproj/ver1/rev1/sdrm.bld vhdl/par/xproj/ver1/rev1/sdrm.dly vhdl/par/xproj/ver1/rev1/sdrm.drc vhdl/par/xproj/ver1/rev1/sdrm.ll vhdl/par/xproj/ver1/rev1/sdrm.ncd vhdl/par/xproj/ver1/rev1/sdrm.nga vhdl/par/xproj/ver1/rev1/sdrm.ngd vhdl/par/xproj/ver1/rev1/sdrm.pad vhdl/par/xproj/ver1/rev1/sdrm.par vhdl/par/xproj/ver1/rev1/sdrm.pcf vhdl/par/xproj/ver1/rev1/sdrm.twr vhdl/par/xproj/ver1/rev1/sdrm.ucf vhdl/par/xproj/ver1/rev1/sdrm.xpi vhdl/par/xproj/ver1/rev1/sdrm_ngdbuild.nav vhdl/par/xproj/ver1/rev1/time_sim.sdf vhdl/par/xproj/ver1/rev1/time_sim.v vhdl/par/xproj/ver1/rev1/time_sim.vhd vhdl/par/xproj/ver1/rev1/virtex.cfg vhdl/par/xproj/ver1/rev1/virtex.imp vhdl/par/xproj/ver1/rev1/virtex.sml vhdl/par/xproj/ver1/sdrm.ngo vhdl/par/xproj/ver1/version.vbf vhdl/post_route/ vhdl/post_route/glbl.v vhdl/post_route/mt48lc1m16a1.v vhdl/post_route/run_sim.do vhdl/post_route/tb_sdrm.v vhdl/post_route/time_sim.sdf vhdl/post_route/time_sim.vhd vhdl/post_route/transcript vhdl/post_route/work/ vhdl/post_route/work/glbl/ vhdl/post_route/work/glbl/verilog.asm vhdl/post_route/work/glbl/_primary.dat vhdl/post_route/work/glbl/_primary.vhd vhdl/post_route/work/mt48lc1m16a1/ vhdl/post_route/work/mt48lc1m16a1/verilog.asm vhdl/post_route/work/mt48lc1m16a1/_primary.dat vhdl/post_route/work/mt48lc1m16a1/_primary.vhd vhdl/post_route/work/roc/ vhdl/post_route/work/roc/roc_v.asm vhdl/post_route/work/roc/roc_v.dat vhdl/post_route/work/roc/_primary.dat vhdl/post_route/work/sdrm/ vhdl/post_route/work/sdrm/structure.asm vhdl/post_route/work/sdrm/structure.dat vhdl/post_route/work/sdrm/_primary.dat vhdl/post_route/work/toc/ vhdl/post_route/work/toc/toc_v.asm vhdl/post_route/work/toc/toc_v.dat vhdl/post_route/work/toc/_primary.dat vhdl/post_route/work/t_sdrm/ vhdl/post_route/work/t_sdrm/verilog.asm vhdl/post_route/work/t_sdrm/_primary.dat vhdl/post_route/work/t_sdrm/_primary.vhd vhdl/post_route/work/_info vhdl/README vhdl/README~ vhdl/src/ vhdl/src/brst_cntr.vhd vhdl/src/cslt_cntr.vhd vhdl/src/ki_cntr.vhd vhdl/src/mti_pkg.vhd vhdl/src/rcd_cntr.vhd vhdl/src/ref_cntr.vhd vhdl/src/sdrm.vhd vhdl/src/sdrmc_state.vhd vhdl/src/sdrm_t.vhd vhdl/src/sys_int.vhd vhdl/synth/ vhdl/synth/brst_cntr.vhd vhdl/synth/cslt_cntr.vhd vhdl/synth/ki_cntr.vhd vhdl/synth/mti_pkg.vhd vhdl/synth/rcd_cntr.vhd vhdl/synth/ref_cntr.vhd vhdl/synth/rev_1/ vhdl/synth/rev_1/sdrm.bit vhdl/synth/rev_1/sdrm.edf vhdl/synth/rev_1/sdrm.ll vhdl/synth/rev_1/sdrm.ncf vhdl/synth/rev_1/sdrm.srm vhdl/synth/rev_1/sdrm.srr vhdl/synth/rev_1/sdrm.srs vhdl/synth/rev_1/sdrm.sxr vhdl/synth/rev_1/sdrm.tlg vhdl/synth/rev_1/xproj/ vhdl/synth/rev_1/xproj/sdrm.xpj vhdl/synth/rev_1/xproj/ver1/ vhdl/synth/rev_1/xproj/ver1/netlist.lst vhdl/synth/rev_1/xproj/ver1/rev1/ vhdl/synth/rev_1/xproj/ver1/rev1/bitgen.ut vhdl/synth/rev_1/xproj/ver1/rev1/command.his vhdl/synth/rev_1/xproj/ver1/rev1/fe.log vhdl/synth/rev_1/xproj/ver1/rev1/map.mrp vhdl/synth/rev_1/xproj/ver1/rev1/map.ncd vhdl/synth/rev_1/xproj/ver1/rev1/map.ngm vhdl/synth/rev_1/xproj/ver1/rev1/program.his vhdl/synth/rev_1/xproj/ver1/rev1/revision.obf vhdl/synth/rev_1/xproj/ver1/rev1/revision.rbf vhdl/synth/rev_1/xproj/ver1/rev1/sdrm.bgn vhdl/synth/rev_1/xproj/ver1/rev1/sdrm.bit vhdl/synth/rev_1/xproj/ver1/rev1/sdrm.bld vhdl/synth/rev_1/xproj/ver1/rev1/sdrm.dly vhdl/synth/rev_1/xproj/ver1/rev1/sdrm.drc vhdl/synth/rev_1/xproj/ver1/rev1/sdrm.ll vhdl/synth/rev_1/xproj/ver1/rev1/sdrm.ncd vhdl/synth/rev_1/xproj/ver1/rev1/sdrm.ngd vhdl/synth/rev_1/xproj/ver1/rev1/sdrm.pad vhdl/synth/rev_1/xproj/ver1/rev1/sdrm.par vhdl/synth/rev_1/xproj/ver1/rev1/sdrm.pcf vhdl/synth/rev_1/xproj/ver1/rev1/sdrm.twr vhdl/synth/rev_1/xproj/ver1/rev1/sdrm.ucf vhdl/synth/rev_1/xproj/ver1/rev1/sdrm.xpi vhdl/synth/rev_1/xproj/ver1/rev1/sdrm_ngdbuild.nav vhdl/synth/rev_1/xproj/ver1/rev1/virtex.cfg vhdl/synth/rev_1/xproj/ver1/rev1/virtex.imp vhdl/synth/rev_1/xproj/ver1/sdrm.ngo vhdl/synth/rev_1/xproj/ver1/version.vbf vhdl/synth/sdrm.vhd vhdl/synth/sdrmc_state.vhd vhdl/synth/sdrm_t.vhd vhdl/synth/sys_int.vhd vhdl/synth/vhdl.prj