文件名称:shizhong

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • 上传时间:
  • 2016-05-28
  • 文件大小:
  • 362kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • 李**
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

这是用VHDL编写的数字逻辑时钟电路,实现计时和由23:59到00:00转换的功能,已经在FPGA中测试通过!-This is written in VHDL digital logic circuit。It can realize the function of timing and by 23:59 to 00:00 conversion, has been in the FPGA test through!
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下载文件列表





shizhong

........\db

........\..\prev_cmp_shuzishizhong.asm.qmsg

........\..\prev_cmp_shuzishizhong.fit.qmsg

........\..\prev_cmp_shuzishizhong.map.qmsg

........\..\prev_cmp_shuzishizhong.qmsg

........\..\prev_cmp_shuzishizhong.tan.qmsg

........\..\shuzishizhong.asm.qmsg

........\..\shuzishizhong.asm_labs.ddb

........\..\shuzishizhong.cbx.xml

........\..\shuzishizhong.cmp.bpm

........\..\shuzishizhong.cmp.cdb

........\..\shuzishizhong.cmp.ecobp

........\..\shuzishizhong.cmp.hdb

........\..\shuzishizhong.cmp.logdb

........\..\shuzishizhong.cmp.rdb

........\..\shuzishizhong.cmp.tdb

........\..\shuzishizhong.cmp0.ddb

........\..\shuzishizhong.cmp2.ddb

........\..\shuzishizhong.cmp_bb.cdb

........\..\shuzishizhong.cmp_bb.hdb

........\..\shuzishizhong.cmp_bb.logdb

........\..\shuzishizhong.cmp_bb.rcf

........\..\shuzishizhong.db_info

........\..\shuzishizhong.dbp

........\..\shuzishizhong.eco.cdb

........\..\shuzishizhong.fit.qmsg

........\..\shuzishizhong.hier_info

........\..\shuzishizhong.hif

........\..\shuzishizhong.map.bpm

........\..\shuzishizhong.map.cdb

........\..\shuzishizhong.map.ecobp

........\..\shuzishizhong.map.hdb

........\..\shuzishizhong.map.logdb

........\..\shuzishizhong.map.qmsg

........\..\shuzishizhong.map_bb.cdb

........\..\shuzishizhong.map_bb.hdb

........\..\shuzishizhong.map_bb.logdb

........\..\shuzishizhong.pre_map.cdb

........\..\shuzishizhong.pre_map.hdb

........\..\shuzishizhong.psp

........\..\shuzishizhong.pss

........\..\shuzishizhong.rtlv.hdb

........\..\shuzishizhong.rtlv_sg.cdb

........\..\shuzishizhong.rtlv_sg_swap.cdb

........\..\shuzishizhong.sgdiff.cdb

........\..\shuzishizhong.sgdiff.hdb

........\..\shuzishizhong.signalprobe.cdb

........\..\shuzishizhong.sld_design_entry.sci

........\..\shuzishizhong.sld_design_entry_dsc.sci

........\..\shuzishizhong.syn_hier_info

........\..\shuzishizhong.tan.qmsg

........\..\shuzishizhong.tis_db_list.ddb

........\shuzishizhong.asm.rpt

........\shuzishizhong.done

........\shuzishizhong.dpf

........\shuzishizhong.fit.rpt

........\shuzishizhong.fit.smsg

........\shuzishizhong.fit.summary

........\shuzishizhong.flow.rpt

........\shuzishizhong.map.rpt

........\shuzishizhong.map.summary

........\shuzishizhong.pin

........\shuzishizhong.pof

........\shuzishizhong.qpf

........\shuzishizhong.qsf

........\shuzishizhong.qws

........\shuzishizhong.sof

........\shuzishizhong.tan.rpt

........\shuzishizhong.tan.summary

........\shuzishizhong.vhd

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