文件名称:clock_design
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数字钟的verilog代码，quartusII开发环境.
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下载文件列表
压缩包 : 77433617clock_design.rar 列表 clock_design\bianma.bsf clock_design\bianma.v clock_design\LED.bsf clock_design\LED.v clock_design\main.bsf clock_design\main.v clock_design\shuzibiao.asm.rpt clock_design\shuzibiao.bdf clock_design\shuzibiao.done clock_design\shuzibiao.fit.rpt clock_design\shuzibiao.fit.smsg clock_design\shuzibiao.fit.summary clock_design\shuzibiao.flow.rpt clock_design\shuzibiao.map.rpt clock_design\shuzibiao.map.summary clock_design\shuzibiao.pin clock_design\shuzibiao.pof clock_design\shuzibiao.qpf clock_design\shuzibiao.qsf clock_design\shuzibiao.qws clock_design\shuzibiao.sim.rpt clock_design\shuzibiao.sof clock_design\shuzibiao.tan.rpt clock_design\shuzibiao.tan.summary clock_design\shuzibiao.vwf clock_design\sopc_builder_debug_log.txt clock_design\db\add_sub_1sh.tdf clock_design\db\shuzibiao.(0).cnf.cdb clock_design\db\shuzibiao.(0).cnf.hdb clock_design\db\shuzibiao.(1).cnf.cdb clock_design\db\shuzibiao.(1).cnf.hdb clock_design\db\shuzibiao.(2).cnf.cdb clock_design\db\shuzibiao.(2).cnf.hdb clock_design\db\shuzibiao.(3).cnf.cdb clock_design\db\shuzibiao.(3).cnf.hdb clock_design\db\shuzibiao.asm.qmsg clock_design\db\shuzibiao.cbx.xml clock_design\db\shuzibiao.cmp.cdb clock_design\db\shuzibiao.cmp.hdb clock_design\db\shuzibiao.cmp.kpt clock_design\db\shuzibiao.cmp.logdb clock_design\db\shuzibiao.cmp.rdb clock_design\db\shuzibiao.cmp.tdb clock_design\db\shuzibiao.cmp0.ddb clock_design\db\shuzibiao.dbp clock_design\db\shuzibiao.db_info clock_design\db\shuzibiao.eco.cdb clock_design\db\shuzibiao.eds_overflow clock_design\db\shuzibiao.fit.qmsg clock_design\db\shuzibiao.fnsim.cdb clock_design\db\shuzibiao.fnsim.hdb clock_design\db\shuzibiao.fnsim.qmsg clock_design\db\shuzibiao.hier_info clock_design\db\shuzibiao.hif clock_design\db\shuzibiao.map.cdb clock_design\db\shuzibiao.map.hdb clock_design\db\shuzibiao.map.logdb clock_design\db\shuzibiao.map.qmsg clock_design\db\shuzibiao.pre_map.cdb clock_design\db\shuzibiao.pre_map.hdb clock_design\db\shuzibiao.psp clock_design\db\shuzibiao.rtlv.hdb clock_design\db\shuzibiao.rtlv_sg.cdb clock_design\db\shuzibiao.rtlv_sg_swap.cdb clock_design\db\shuzibiao.sgdiff.cdb clock_design\db\shuzibiao.sgdiff.hdb clock_design\db\shuzibiao.signalprobe.cdb clock_design\db\shuzibiao.sim.hdb clock_design\db\shuzibiao.sim.qmsg clock_design\db\shuzibiao.sim.rdb clock_design\db\shuzibiao.sim.vwf clock_design\db\shuzibiao.sld_design_entry.sci clock_design\db\shuzibiao.sld_design_entry_dsc.sci clock_design\db\shuzibiao.smp_dump.txt clock_design\db\shuzibiao.syn_hier_info clock_design\db\shuzibiao.tan.qmsg clock_design\db\wed.zsf clock_design\.sopc_builder\install.ptf clock_design\db clock_design\.sopc_builder clock_design