文件名称:8086vga
介绍说明－－下载内容均来自于网络，请自行研究使用
：两人乒乓球赛
Requires: D2SB and DIO4 with VGA monitor and PS2 Keyboard
Requires: D2SB and DIO4 with VGA monitor and PS2 Keyboard
(系统自动生成,下载前可以参看下载内容)
下载文件列表
压缩包 : 516224228086vga.rar 列表 8086vga\.lso 8086vga\8086vga.ise 8086vga\8086vga.ise_ISE_Backup 8086vga\8086vga.ntrc_log 8086vga\CPU\alu\rtl.dat 8086vga\CPU\alu\_primary.dat 8086vga\CPU\a_table\rtl.dat 8086vga\CPU\a_table\_primary.dat 8086vga\CPU\biu\struct.dat 8086vga\CPU\biu\_primary.dat 8086vga\CPU\biufsm\fsm.dat 8086vga\CPU\biufsm\_primary.dat 8086vga\CPU\cpu86\struct.dat 8086vga\CPU\cpu86\_primary.dat 8086vga\CPU\cpu86instr\_primary.dat 8086vga\CPU\cpu86pack\_primary.dat 8086vga\CPU\datapath\struct.dat 8086vga\CPU\datapath\_primary.dat 8086vga\CPU\dataregfile\rtl.dat 8086vga\CPU\dataregfile\_primary.dat 8086vga\CPU\divider\rtl_ser.dat 8086vga\CPU\divider\_primary.dat 8086vga\CPU\d_table\rtl.dat 8086vga\CPU\d_table\_primary.dat 8086vga\CPU\formatter\struct.dat 8086vga\CPU\formatter\_primary.dat 8086vga\CPU\hwmfsm\fsm.dat 8086vga\CPU\hwmfsm\_primary.dat 8086vga\CPU\hwmon\struct.dat 8086vga\CPU\hwmon\_primary.dat 8086vga\CPU\ipregister\rtl.dat 8086vga\CPU\ipregister\_primary.dat 8086vga\CPU\multiplier\rtl.dat 8086vga\CPU\multiplier\_primary.dat 8086vga\CPU\m_table\rtl.dat 8086vga\CPU\m_table\_primary.dat 8086vga\CPU\n_table\rtl.dat 8086vga\CPU\n_table\_primary.dat 8086vga\CPU\proc\rtl.dat 8086vga\CPU\proc\_primary.dat 8086vga\CPU\regshiftmux\regshift.dat 8086vga\CPU\regshiftmux\_primary.dat 8086vga\CPU\r_table\rtl.dat 8086vga\CPU\r_table\_primary.dat 8086vga\CPU\segregfile\rtl.dat 8086vga\CPU\segregfile\_primary.dat 8086vga\CPU\_info 8086vga\cpu86.vhd 8086vga\device_usage_statistics.html 8086vga\disp.vhd 8086vga\disp_ram.asy 8086vga\disp_ram.edn 8086vga\disp_ram.sym 8086vga\disp_ram.v 8086vga\disp_ram.veo 8086vga\disp_ram.vhd 8086vga\disp_ram.vho 8086vga\disp_ram.xco 8086vga\disp_ram_flist.txt 8086vga\embedded_rom.asy 8086vga\embedded_rom.edn 8086vga\embedded_rom.mif 8086vga\embedded_rom.sym 8086vga\embedded_rom.v 8086vga\embedded_rom.veo 8086vga\embedded_rom.vhd 8086vga\embedded_rom.vho 8086vga\embedded_rom.xco 8086vga\embedded_rom_dist_mem_gen_v3_2_xst_1.ngc 8086vga\embedded_rom_flist.txt 8086vga\myclock.xaw 8086vga\pepExtractor.prj 8086vga\pio_rtl.vhd 8086vga\rom.coe 8086vga\superio_top_struct.vhd 8086vga\templates\coregen.xml 8086vga\textram.asy 8086vga\textram.coe 8086vga\textram.edn 8086vga\textram.mif 8086vga\textram.sym 8086vga\textram.v 8086vga\textram.veo 8086vga\textram.vhd 8086vga\textram.vho 8086vga\textram.xco 8086vga\textram_flist.txt 8086vga\timer_fsm_fsm.vhd 8086vga\timer_top_struct.vhd 8086vga\top.bit 8086vga\Top.ucf 8086vga\Top.ut 8086vga\Top_prev_built.ngd 8086vga\top_struct.vhd 8086vga\Top_summary.html 8086vga\uartrx.vhd 8086vga\uarttx.vhd 8086vga\uart_struct.vhd 8086vga\work\disp\behavioral.dat 8086vga\work\disp\_primary.dat 8086vga\work\disp_ram\disp_ram_a.dat 8086vga\work\disp_ram\_primary.dat 8086vga\work\disp_ram\_primary.vhd 8086vga\work\embedded_rom\embedded_rom_a.dat 8086vga\work\embedded_rom\_primary.dat 8086vga\work\glbl\_primary.dat 8086vga\work\glbl\_primary.vhd 8086vga\work\myclock\behavioral.dat 8086vga\work\myclock\_primary.dat 8086vga\work\myclock\_primary.vhd 8086vga\work\pio\rtl.dat 8086vga\work\pio\_primary.dat 8086vga\work\sram32kx16\behaviour.dat 8086vga\work\sram32kx16\_primary.dat 8086vga\work\superio_top\struct.dat 8086vga\work\superio_top\_primary.dat 8086vga\work\tester\behaviour.dat 8086vga\work\tester\_primary.dat 8086vga\work\textram\textram_a.dat 8086vga\work\textram\_primary.dat 8086vga\work\textram\_primary.vhd 8086vga\work\timer_fsm\fsm.dat 8086vga\work\timer_fsm\_primary.dat 8086vga\work\timer_top\struct.dat 8086vga\work\timer_top\_primary.dat 8086vga\work\top\struct.dat 8086vga\work\top\_primary.dat 8086vga\work\top_tb\struct.dat 8086vga\work\top_tb\_primary.dat 8086vga\work\uart\struct.dat 8086vga\work\uart\_primary.dat 8086vga\work\uartrx\rtl.dat 8086vga\work\uartrx\_primary.dat 8086vga\work\uarttx\rtl.dat 8086vga\work\uarttx\_primary.dat 8086vga\work\utils\body.dat 8086vga\work\utils\_primary.dat 8086vga\work\_info 8086vga\work\_opt\work_tester_behaviour.asm 8086vga\work\_opt\work_uarttx_rtl.asm 8086vga\work\_opt\work_utils_body.asm 8086vga\work\_opt\work_utils__vhdl.asm 8086vga\work\_opt\work__info 8086vga\work\_opt\_deps 8086vga\work\_opt\__model_tech_.._ieee__info 8086vga\work\_opt\__model_tech_.._std__info 8086vga\work\_opt1\cpu_alu_rtl__1.asm 8086vga\work\_opt1\cpu_a_table_rtl.asm 8086vga\work\_opt1\cpu_biufsm_fsm.asm 8086vga\work\_opt1\cpu_biu_struct.asm 8086vga\work\_opt1\cpu_cpu86instr__vhdl.asm 8086vga\work\_opt1\cpu_cpu86pack__vhdl.asm 8086vga\work\_opt1\cpu_cpu86_struct__1.asm 8086vga\work\_opt1\cpu_datapath_struct__1.asm 8086vga\work\_opt1\cpu_dataregfile_rtl.asm 8086vga\work\_opt1\cpu_divider_rtl_ser__1.asm 8086vga\work\_opt1\cpu_d_table_rtl.asm 8086vga\work\_opt1\cpu_formatter_struct.asm 8086vga\work\_opt1\cpu_ipregister_rtl.asm 8086vga\work\_opt1\cpu_multiplier_rtl__1.asm 8086vga\work\_opt1\cpu_m_table_rtl.asm 8086vga\work\_opt1\cpu_n_table_rtl.asm 8086vga\work\_opt1\cpu_proc_rtl.asm 8086vga\work\_opt1\cpu_regshiftmux_regshift.asm 8086vga\work\_opt1\cpu_r_table_rtl.asm 8086vga\work\_opt1\cpu_segregfile_rtl.asm 8086vga\work\_opt1\cpu__info 8086vga\work\_opt1\d__Modeltech_6.2b_xilinx_libs_unisims_ver_@b@u@f@g_fast.dt2 8086vga\work\_opt1\d__Modeltech_6.2b_xilinx_libs_unisims_ver_@d@c@m_@s@p_fast.dt2 8086vga\work\_opt1\d__Modeltech_6.2b_xilinx_libs_unisims_ver_dcm_sp_clock_divide_by_2_fast.dt2 8086vga\work\_opt1\d__Modeltech_6.2b_xilinx_libs_unisims_ver_dcm_sp_clock_lost_fast.dt2 8086vga\work\_opt1\d__Modeltech_6.2b_xilinx_libs_unisims_ver_dcm_sp_maximum_period_check_fast.dt2 8086vga\work\_opt1\d__Modeltech_6.2b_xilinx_libs_unisims_ver_dcm_sp_maximum_period_check_fast__1.dt2 8086vga\work\_opt1\d__Modeltech_6.2b_xilinx_libs_unisims_ver__info 8086vga\work\_opt1\d__Modeltech_6.2b_xilinx_libs_XilinxCoreLib_ver_@b@l@k@m@e@m@d@p_@v6_3_fast.asm 8086vga\work\_opt1\d__Modeltech_6.2b_xilinx_libs_XilinxCoreLib_ver_@b@l@k@m@e@m@d@p_@v6_3_fast.dt2 8086vga\work\_opt1\d__Modeltech_6.2b_xilinx_libs_XilinxCoreLib_ver_@b@l@k@m@e@m@s@p_@v6_2_fast.dt2 8086vga\work\_opt1\d__Modeltech_6.2b_xilinx_libs_XilinxCoreLib_ver__info 8086vga\work\_opt1\work_disp_behavioral.asm 8086vga\work\_opt1\work_disp_ram_fast.asm 8086vga\work\_opt1\work_disp_ram_fast.dt2 8086vga\work\_opt1\work_glbl_fast.asm 8086vga\work\_opt1\work_glbl_fast.dt2 8086vga\work\_opt1\work_myclock_fast.asm 8086vga\work\_opt1\work_myclock_fast.dt2 8086vga\work\_opt1\work_pio_rtl.asm 8086vga\work\_opt1\work_superio_top_struct__1.asm 8086vga\work\_opt1\work_textram_fast.asm 8086vga\work\_opt1\work_textram_fast.dt2 8086vga\work\_opt1\work_timer_fsm_fsm.asm 8086vga\work\_opt1\work_timer_top_struct__1.asm 8086vga\work\_opt1\work_top_struct__1.asm 8086vga\work\_opt1\work_uartrx_rtl.asm 8086vga\work\_opt1\work_uarttx_rtl.asm 8086vga\work\_opt1\work_uart_struct__1.asm 8086vga\work\_opt1\work__info 8086vga\work\_opt1\_deps 8086vga\work\_opt1\__model_tech_.._ieee__info 8086vga\work\_opt1\__model_tech_.._std__info 8086vga\work\_opt1\__model_tech_.._verilog__info 8086vga\work\_opt2\cpu_alu_rtl__1.asm 8086vga\work\_opt2\cpu_a_table_rtl.asm 8086vga\work\_opt2\cpu_biufsm_fsm.asm 8086vga\work\_opt2\cpu_biu_struct.asm 8086vga\work\_opt2\cpu_cpu86instr__vhdl.asm 8086vga\work\_opt2\cpu_cpu86pack__vhdl.asm 8086vga\work\_opt2\cpu_cpu86_struct__1.asm 8086vga\work\_opt2\cpu_datapath_struct__1.asm 8086vga\work\_opt2\cpu_dataregfile_rtl.asm 8086vga\work\_opt2\cpu_divider_rtl_ser__1.asm 8086vga\work\_opt2\cpu_d_table_rtl.asm 8086vga\work\_opt2\cpu_formatter_struct.asm 8086vga\work\_opt2\cpu_ipregister_rtl.asm 8086vga\work\_opt2\cpu_multiplier_rtl__1.asm 8086vga\work\_opt2\cpu_m_table_rtl.asm 8086vga\work\_opt2\cpu_n_table_rtl.asm 8086vga\work\_opt2\cpu_proc_rtl.asm 8086vga\work\_opt2\cpu_regshiftmux_regshift.asm 8086vga\work\_opt2\cpu_r_table_rtl.asm 8086vga\work\_opt2\cpu_segregfile_rtl.asm 8086vga\work\_opt2\cpu__info 8086vga\work\_opt2\d__Modeltech_6.2b_xilinx_libs_unisim_bufg_bufg_v.asm 8086vga\work\_opt2\d__Modeltech_6.2b_xilinx_libs_unisim_dcm_sp_clock_divide_by_2_dcm_sp_clock_divide_by_2_v.asm 8086vga\work\_opt2\d__Modeltech_6.2b_xilinx_libs_unisim_dcm_sp_clock_lost_dcm_sp_clock_lost_v.asm 8086vga\work\_opt2\d__Modeltech_6.2b_xilinx_libs_unisim_dcm_sp_dcm_sp_v__1.asm 8086vga\work\_opt2\d__Modeltech_6.2b_xilinx_libs_unisim_dcm_sp_maximum_period_check_dcm_sp_maximum_period_check_v.asm 8086vga\work\_opt2\d__Modeltech_6.2b_xilinx_libs_unisim_vcomponents__vhdl.asm 8086vga\work\_opt2\d__Modeltech_6.2b_xilinx_libs_unisim_vpkg_body.asm 8086vga\work\_opt2\d__Modeltech_6.2b_xilinx_libs_unisim_vpkg__vhdl.asm 8086vga\work\_opt2\d__Modeltech_6.2b_xilinx_libs_unisim__info 8086vga\work\_opt2\d__Modeltech_6.2b_xilinx_libs_XilinxCoreLib_blkmemdp_mem_init_file_pack_v6_3_body.asm 8086vga\work\_opt2\d__Modeltech_6.2b_xilinx_libs_XilinxCoreLib_blkmemdp_mem_init_file_pack_v6_3__vhdl.asm 8086vga\work\_opt2\d__Modeltech_6.2b_xilinx_libs_XilinxCoreLib_blkmemdp_pkg_v6_3_body.asm 8086vga\work\_opt2\d__Modeltech_6.2b_xilinx_libs_XilinxCoreLib_blkmemdp_pkg_v6_3__vhdl.asm 8086vga\work\_opt2\d__Modeltech_6.2b_xilinx_libs_XilinxCoreLib_blkmemdp_v6_3_behavioral__1.asm 8086vga\work\_opt2\d__Modeltech_6.2b_xilinx_libs_XilinxCoreLib_blkmemsp_pkg_v6_2_body.asm 8086vga\work\_opt2\d__Modeltech_6.2b_xilinx_libs_XilinxCoreLib_blkmemsp_pkg_v6_2__vhdl.asm 8086vga\work\_opt2\d__Modeltech_6.2b_xilinx_libs_XilinxCoreLib_blkmemsp_v6_2_behavioral__1.asm 8086vga\work\_opt2\d__Modeltech_6.2b_xilinx_libs_XilinxCoreLib_blkmemsp_v6_2_behavioral__2.asm 8086vga\work\_opt2\d__Modeltech_6.2b_xilinx_libs_XilinxCoreLib_iputils_conv_body.asm 8086vga\work\_opt2\d__Modeltech_6.2b_xilinx_libs_XilinxCoreLib_iputils_conv__vhdl.asm 8086vga\work\_opt2\d__Modeltech_6.2b_xilinx_libs_XilinxCoreLib_mem_init_file_pack_v6_2_body.asm 8086vga\work\_opt2\d__Modeltech_6.2b_xilinx_libs_XilinxCoreLib_mem_init_file_pack_v6_2__vhdl.asm 8086vga\work\_opt2\d__Modeltech_6.2b_xilinx_libs_XilinxCoreLib_ul_utils_body.asm 8086vga\work\_opt2\d__Modeltech_6.2b_xilinx_libs_XilinxCoreLib_ul_utils__vhdl.asm 8086vga\work\_opt2\d__Modeltech_6.2b_xilinx_libs_XilinxCoreLib__info 8086vga\work\_opt2\work_disp_behavioral.asm 8086vga\work\_opt2\work_disp_ram_disp_ram_a__1.asm 8086vga\work\_opt2\work_embedded_rom_embedded_rom_a__1.asm 8086vga\work\_opt2\work_myclock_behavioral__1.asm 8086vga\work\_opt2\work_pio_rtl.asm 8086vga\work\_opt2\work_sram32kx16_behaviour.asm 8086vga\work\_opt2\work_superio_top_struct__1.asm 8086vga\work\_opt2\work_tester_behaviour.asm 8086vga\work\_opt2\work_textram_textram_a__1.asm 8086vga\work\_opt2\work_timer_fsm_fsm.asm 8086vga\work\_opt2\work_timer_top_struct__1.asm 8086vga\work\_opt2\work_top_struct__1.asm 8086vga\work\_opt2\work_top_tb_struct__1.asm 8086vga\work\_opt2\work_uartrx_rtl.asm 8086vga\work\_opt2\work_uarttx_rtl.asm 8086vga\work\_opt2\work_uart_struct__1.asm 8086vga\work\_opt2\work_utils_body.asm 8086vga\work\_opt2\work_utils__vhdl.asm 8086vga\work\_opt2\work__info 8086vga\work\_opt2\_deps 8086vga\work\_opt2\__model_tech_.._ieee__info 8086vga\work\_opt2\__model_tech_.._std__info 8086vga\CPU\alu 8086vga\CPU\a_table 8086vga\CPU\biu 8086vga\CPU\biufsm 8086vga\CPU\cpu86 8086vga\CPU\cpu86instr 8086vga\CPU\cpu86pack 8086vga\CPU\datapath 8086vga\CPU\dataregfile 8086vga\CPU\divider 8086vga\CPU\d_table 8086vga\CPU\formatter 8086vga\CPU\hwmfsm 8086vga\CPU\hwmon 8086vga\CPU\ipregister 8086vga\CPU\multiplier 8086vga\CPU\m_table 8086vga\CPU\n_table 8086vga\CPU\proc 8086vga\CPU\regshiftmux 8086vga\CPU\r_table 8086vga\CPU\segregfile 8086vga\CPU\_temp 8086vga\work\disp 8086vga\work\disp_ram 8086vga\work\embedded_rom 8086vga\work\glbl 8086vga\work\myclock 8086vga\work\pio 8086vga\work\sram32kx16 8086vga\work\superio_top 8086vga\work\tester 8086vga\work\textram 8086vga\work\timer_fsm 8086vga\work\timer_top 8086vga\work\top 8086vga\work\top_tb 8086vga\work\uart 8086vga\work\uartrx 8086vga\work\uarttx 8086vga\work\utils 8086vga\work\_opt 8086vga\work\_opt1 8086vga\work\_opt2 8086vga\work\_temp 8086vga\CPU 8086vga\templates 8086vga\work 8086vga\_cg 8086vga\_xmsgs 8086vga