文件名称:CPU
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计算机组织与结构课程设计，使用VHDL设计一个简单功能的CPU。该CPU拥有基本的指令集，并且能够使用指令集运行简单的程序。另外，CPU的控制器部分（CU）采用微程序设计方式。(The purpose of this project is to design a simple CPU (Central Processing Unit). This CPU has basic instruction set, and we will utilize its instruction set to generate a very simple program to verify its performance. For simplicity, we will only consider the relationship among the CPU, registers, memory and instruction set. That is to say we only need consider the following items: Read/Write Registers, Read/Write Memory and Execute the instructions. )
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下载文件列表
CPU\.lso
CPU\alu.vhd
CPU\ALU_isim_beh.exe
CPU\ALU_isim_beh1.wdb
CPU\ALU_summary.html
CPU\BR.vhd
CPU\CPU.gise
CPU\CPU.xise
CPU\cu.vhd
CPU\CU_isim_beh.exe
CPU\fdiv.lso
CPU\fdiv.prj
CPU\fdiv.stx
CPU\fdiv.vhd
CPU\fdiv.xst
CPU\fdiv_isim_beh.exe
CPU\fdiv_vhdl.prj
CPU\fuse.log
CPU\fuse.xmsgs
CPU\fuseRelaunch.cmd
CPU\impact.xsl
CPU\impact_impact.xwbt
CPU\ipcore_dir\coregen.cgp
CPU\ipcore_dir\coregen.log
CPU\ipcore_dir\create_memory.tcl
CPU\ipcore_dir\dist_mem_gen_v7_2\dist_mem_gen_v7_2_readme.txt
CPU\ipcore_dir\dist_mem_gen_v7_2\doc\dist_mem_gen_v7_2_vinfo.html
CPU\ipcore_dir\dist_mem_gen_v7_2\doc\pg063-dist-mem-gen.pdf
CPU\ipcore_dir\dist_mem_gen_v7_2\example_design\dist_mem_gen_v7_2_exdes.ucf
CPU\ipcore_dir\dist_mem_gen_v7_2\example_design\dist_mem_gen_v7_2_exdes.vhd
CPU\ipcore_dir\dist_mem_gen_v7_2\example_design\dist_mem_gen_v7_2_exdes.xdc
CPU\ipcore_dir\dist_mem_gen_v7_2\example_design\dist_mem_gen_v7_2_prod_exdes.vhd
CPU\ipcore_dir\dist_mem_gen_v7_2\implement\implement.bat
CPU\ipcore_dir\dist_mem_gen_v7_2\implement\implement.sh
CPU\ipcore_dir\dist_mem_gen_v7_2\implement\implement_synplify.bat
CPU\ipcore_dir\dist_mem_gen_v7_2\implement\implement_synplify.sh
CPU\ipcore_dir\dist_mem_gen_v7_2\implement\planAhead_ise.bat
CPU\ipcore_dir\dist_mem_gen_v7_2\implement\planAhead_ise.sh
CPU\ipcore_dir\dist_mem_gen_v7_2\implement\planAhead_ise.tcl
CPU\ipcore_dir\dist_mem_gen_v7_2\implement\xst.prj
CPU\ipcore_dir\dist_mem_gen_v7_2\implement\xst.scr
CPU\ipcore_dir\dist_mem_gen_v7_2\simulation\dist_mem_gen_v7_2_tb.vhd
CPU\ipcore_dir\dist_mem_gen_v7_2\simulation\dist_mem_gen_v7_2_tb_agen.vhd
CPU\ipcore_dir\dist_mem_gen_v7_2\simulation\dist_mem_gen_v7_2_tb_checker.vhd
CPU\ipcore_dir\dist_mem_gen_v7_2\simulation\dist_mem_gen_v7_2_tb_dgen.vhd
CPU\ipcore_dir\dist_mem_gen_v7_2\simulation\dist_mem_gen_v7_2_tb_pkg.vhd
CPU\ipcore_dir\dist_mem_gen_v7_2\simulation\dist_mem_gen_v7_2_tb_rng.vhd
CPU\ipcore_dir\dist_mem_gen_v7_2\simulation\dist_mem_gen_v7_2_tb_stim_gen.vhd
CPU\ipcore_dir\dist_mem_gen_v7_2\simulation\dist_mem_gen_v7_2_tb_synth.vhd
CPU\ipcore_dir\dist_mem_gen_v7_2\simulation\functional\simulate_mti.bat
CPU\ipcore_dir\dist_mem_gen_v7_2\simulation\functional\simulate_mti.do
CPU\ipcore_dir\dist_mem_gen_v7_2\simulation\functional\simulate_mti.sh
CPU\ipcore_dir\dist_mem_gen_v7_2\simulation\timing\simulate_mti.bat
CPU\ipcore_dir\dist_mem_gen_v7_2\simulation\timing\simulate_mti.do
CPU\ipcore_dir\dist_mem_gen_v7_2\simulation\timing\simulate_mti.sh
CPU\ipcore_dir\dist_mem_gen_v7_2.asy
CPU\ipcore_dir\dist_mem_gen_v7_2.gise
CPU\ipcore_dir\dist_mem_gen_v7_2.mif
CPU\ipcore_dir\dist_mem_gen_v7_2.ngc
CPU\ipcore_dir\dist_mem_gen_v7_2.sym
CPU\ipcore_dir\dist_mem_gen_v7_2.vhd
CPU\ipcore_dir\dist_mem_gen_v7_2.vho
CPU\ipcore_dir\dist_mem_gen_v7_2.xco
CPU\ipcore_dir\dist_mem_gen_v7_2.xise
CPU\ipcore_dir\dist_mem_gen_v7_2_flist.txt
CPU\ipcore_dir\dist_mem_gen_v7_2_xmdf.tcl
CPU\ipcore_dir\edit_memory.tcl
CPU\ipcore_dir\gen_memory.tcl
CPU\ipcore_dir\memory\dist_mem_gen_v7_2_readme.txt
CPU\ipcore_dir\memory\doc\dist_mem_gen_v7_2_vinfo.html
CPU\ipcore_dir\memory\doc\pg063-dist-mem-gen.pdf
CPU\ipcore_dir\memory\example_design\memory_exdes.ucf
CPU\ipcore_dir\memory\example_design\memory_exdes.vhd
CPU\ipcore_dir\memory\example_design\memory_exdes.xdc
CPU\ipcore_dir\memory\example_design\memory_prod_exdes.vhd
CPU\ipcore_dir\memory\implement\implement.bat
CPU\ipcore_dir\memory\implement\implement.sh
CPU\ipcore_dir\memory\implement\implement_synplify.bat
CPU\ipcore_dir\memory\implement\implement_synplify.sh
CPU\ipcore_dir\memory\implement\planAhead_ise.bat
CPU\ipcore_dir\memory\implement\planAhead_ise.sh
CPU\ipcore_dir\memory\implement\planAhead_ise.tcl
CPU\ipcore_dir\memory\implement\xst.prj
CPU\ipcore_dir\memory\implement\xst.scr
CPU\ipcore_dir\memory\simulation\functional\simulate_mti.bat
CPU\ipcore_dir\memory\simulation\functional\simulate_mti.do
CPU\ipcore_dir\memory\simulation\functional\simulate_mti.sh
CPU\ipcore_dir\memory\simulation\memory_tb.vhd
CPU\ipcore_dir\memory\simulation\memory_tb_agen.vhd
CPU\ipcore_dir\memory\simulation\memory_tb_checker.vhd
CPU\ipcore_dir\memory\simulation\memory_tb_dgen.vhd
CPU\ipcore_dir\memory\simulation\memory_tb_pkg.vhd
CPU\ipcore_dir\memory\simulation\memory_tb_rng.vhd
CPU\ipcore_dir\memory\simulation\memory_tb_stim_gen.vhd
CPU\ipcore_dir\memory\simulation\memory_tb_synth.vhd
CPU\ipcore_dir\memory\simulation\timing\simulate_mti.bat
CPU\ipcore_dir\memory\simulation\timing\simulate_mti.do
CPU\ipcore_dir\memory\simulation\timing\simulate_mti.sh
CPU\ipcore_dir\memory.asy
CPU\ipcore_dir\memory.gise
CPU\alu.vhd
CPU\ALU_isim_beh.exe
CPU\ALU_isim_beh1.wdb
CPU\ALU_summary.html
CPU\BR.vhd
CPU\CPU.gise
CPU\CPU.xise
CPU\cu.vhd
CPU\CU_isim_beh.exe
CPU\fdiv.lso
CPU\fdiv.prj
CPU\fdiv.stx
CPU\fdiv.vhd
CPU\fdiv.xst
CPU\fdiv_isim_beh.exe
CPU\fdiv_vhdl.prj
CPU\fuse.log
CPU\fuse.xmsgs
CPU\fuseRelaunch.cmd
CPU\impact.xsl
CPU\impact_impact.xwbt
CPU\ipcore_dir\coregen.cgp
CPU\ipcore_dir\coregen.log
CPU\ipcore_dir\create_memory.tcl
CPU\ipcore_dir\dist_mem_gen_v7_2\dist_mem_gen_v7_2_readme.txt
CPU\ipcore_dir\dist_mem_gen_v7_2\doc\dist_mem_gen_v7_2_vinfo.html
CPU\ipcore_dir\dist_mem_gen_v7_2\doc\pg063-dist-mem-gen.pdf
CPU\ipcore_dir\dist_mem_gen_v7_2\example_design\dist_mem_gen_v7_2_exdes.ucf
CPU\ipcore_dir\dist_mem_gen_v7_2\example_design\dist_mem_gen_v7_2_exdes.vhd
CPU\ipcore_dir\dist_mem_gen_v7_2\example_design\dist_mem_gen_v7_2_exdes.xdc
CPU\ipcore_dir\dist_mem_gen_v7_2\example_design\dist_mem_gen_v7_2_prod_exdes.vhd
CPU\ipcore_dir\dist_mem_gen_v7_2\implement\implement.bat
CPU\ipcore_dir\dist_mem_gen_v7_2\implement\implement.sh
CPU\ipcore_dir\dist_mem_gen_v7_2\implement\implement_synplify.bat
CPU\ipcore_dir\dist_mem_gen_v7_2\implement\implement_synplify.sh
CPU\ipcore_dir\dist_mem_gen_v7_2\implement\planAhead_ise.bat
CPU\ipcore_dir\dist_mem_gen_v7_2\implement\planAhead_ise.sh
CPU\ipcore_dir\dist_mem_gen_v7_2\implement\planAhead_ise.tcl
CPU\ipcore_dir\dist_mem_gen_v7_2\implement\xst.prj
CPU\ipcore_dir\dist_mem_gen_v7_2\implement\xst.scr
CPU\ipcore_dir\dist_mem_gen_v7_2\simulation\dist_mem_gen_v7_2_tb.vhd
CPU\ipcore_dir\dist_mem_gen_v7_2\simulation\dist_mem_gen_v7_2_tb_agen.vhd
CPU\ipcore_dir\dist_mem_gen_v7_2\simulation\dist_mem_gen_v7_2_tb_checker.vhd
CPU\ipcore_dir\dist_mem_gen_v7_2\simulation\dist_mem_gen_v7_2_tb_dgen.vhd
CPU\ipcore_dir\dist_mem_gen_v7_2\simulation\dist_mem_gen_v7_2_tb_pkg.vhd
CPU\ipcore_dir\dist_mem_gen_v7_2\simulation\dist_mem_gen_v7_2_tb_rng.vhd
CPU\ipcore_dir\dist_mem_gen_v7_2\simulation\dist_mem_gen_v7_2_tb_stim_gen.vhd
CPU\ipcore_dir\dist_mem_gen_v7_2\simulation\dist_mem_gen_v7_2_tb_synth.vhd
CPU\ipcore_dir\dist_mem_gen_v7_2\simulation\functional\simulate_mti.bat
CPU\ipcore_dir\dist_mem_gen_v7_2\simulation\functional\simulate_mti.do
CPU\ipcore_dir\dist_mem_gen_v7_2\simulation\functional\simulate_mti.sh
CPU\ipcore_dir\dist_mem_gen_v7_2\simulation\timing\simulate_mti.bat
CPU\ipcore_dir\dist_mem_gen_v7_2\simulation\timing\simulate_mti.do
CPU\ipcore_dir\dist_mem_gen_v7_2\simulation\timing\simulate_mti.sh
CPU\ipcore_dir\dist_mem_gen_v7_2.asy
CPU\ipcore_dir\dist_mem_gen_v7_2.gise
CPU\ipcore_dir\dist_mem_gen_v7_2.mif
CPU\ipcore_dir\dist_mem_gen_v7_2.ngc
CPU\ipcore_dir\dist_mem_gen_v7_2.sym
CPU\ipcore_dir\dist_mem_gen_v7_2.vhd
CPU\ipcore_dir\dist_mem_gen_v7_2.vho
CPU\ipcore_dir\dist_mem_gen_v7_2.xco
CPU\ipcore_dir\dist_mem_gen_v7_2.xise
CPU\ipcore_dir\dist_mem_gen_v7_2_flist.txt
CPU\ipcore_dir\dist_mem_gen_v7_2_xmdf.tcl
CPU\ipcore_dir\edit_memory.tcl
CPU\ipcore_dir\gen_memory.tcl
CPU\ipcore_dir\memory\dist_mem_gen_v7_2_readme.txt
CPU\ipcore_dir\memory\doc\dist_mem_gen_v7_2_vinfo.html
CPU\ipcore_dir\memory\doc\pg063-dist-mem-gen.pdf
CPU\ipcore_dir\memory\example_design\memory_exdes.ucf
CPU\ipcore_dir\memory\example_design\memory_exdes.vhd
CPU\ipcore_dir\memory\example_design\memory_exdes.xdc
CPU\ipcore_dir\memory\example_design\memory_prod_exdes.vhd
CPU\ipcore_dir\memory\implement\implement.bat
CPU\ipcore_dir\memory\implement\implement.sh
CPU\ipcore_dir\memory\implement\implement_synplify.bat
CPU\ipcore_dir\memory\implement\implement_synplify.sh
CPU\ipcore_dir\memory\implement\planAhead_ise.bat
CPU\ipcore_dir\memory\implement\planAhead_ise.sh
CPU\ipcore_dir\memory\implement\planAhead_ise.tcl
CPU\ipcore_dir\memory\implement\xst.prj
CPU\ipcore_dir\memory\implement\xst.scr
CPU\ipcore_dir\memory\simulation\functional\simulate_mti.bat
CPU\ipcore_dir\memory\simulation\functional\simulate_mti.do
CPU\ipcore_dir\memory\simulation\functional\simulate_mti.sh
CPU\ipcore_dir\memory\simulation\memory_tb.vhd
CPU\ipcore_dir\memory\simulation\memory_tb_agen.vhd
CPU\ipcore_dir\memory\simulation\memory_tb_checker.vhd
CPU\ipcore_dir\memory\simulation\memory_tb_dgen.vhd
CPU\ipcore_dir\memory\simulation\memory_tb_pkg.vhd
CPU\ipcore_dir\memory\simulation\memory_tb_rng.vhd
CPU\ipcore_dir\memory\simulation\memory_tb_stim_gen.vhd
CPU\ipcore_dir\memory\simulation\memory_tb_synth.vhd
CPU\ipcore_dir\memory\simulation\timing\simulate_mti.bat
CPU\ipcore_dir\memory\simulation\timing\simulate_mti.do
CPU\ipcore_dir\memory\simulation\timing\simulate_mti.sh
CPU\ipcore_dir\memory.asy
CPU\ipcore_dir\memory.gise