文件名称:an501_design_example
介绍说明－－下载内容均来自于网络，请自行研究使用
VHDL语言实现PWM信号，非常方便的使用
(系统自动生成,下载前可以参看下载内容)
下载文件列表
压缩包 : 17869338an501_design_example.rar 列表 an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\code\pwm_main.v an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\pulse_width_modulator.cr.mti an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\pulse_width_modulator.mpf an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\pwm_main.v an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\pwm_sim.cr.mti an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\pwm_sim.mpf an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\test_pwm.v an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\wave.bmp an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\wave.do an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\wave2.bmp an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\wave2.do an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\wave3.bmp an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\wave3.do an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\wave4.bmp an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\wave4.do an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\wave5.bmp an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\wave5.do an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\altufm_osc0_altufm_osc_1p3\verilog.asm an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\altufm_osc0_altufm_osc_1p3\_primary.dat an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\altufm_osc0_altufm_osc_1p3\_primary.vhd an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\clkgen\verilog.asm an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\clkgen\_primary.dat an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\clkgen\_primary.vhd an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\clk_gen\verilog.asm an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\clk_gen\_primary.dat an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\clk_gen\_primary.vhd an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\dutycycle\verilog.asm an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\dutycycle\_primary.dat an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\dutycycle\_primary.vhd an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\duty_cycle\verilog.asm an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\duty_cycle\_primary.dat an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\duty_cycle\_primary.vhd an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\pwm_gen\verilog.asm an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\pwm_gen\_primary.dat an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\pwm_gen\_primary.vhd an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\pwm_main\verilog.asm an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\pwm_main\_primary.dat an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\pwm_main\_primary.vhd an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\test_pwm\verilog.asm an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\test_pwm\_primary.dat an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\test_pwm\_primary.vhd an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\_info an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.(0).cnf.cdb an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.(0).cnf.hdb an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.(1).cnf.cdb an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.(1).cnf.hdb an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.(2).cnf.cdb an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.(2).cnf.hdb an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.(3).cnf.cdb an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.(3).cnf.hdb an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.(4).cnf.cdb an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.(4).cnf.hdb an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.asm.qmsg an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.asm_labs.ddb an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.cbx.xml an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.cmp.cdb an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.cmp.hdb an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.cmp.logdb an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.cmp.rdb an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.cmp.tdb an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.cmp0.ddb an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.dbp an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.db_info an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.fit.qmsg an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.hier_info an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.hif an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.map.cdb an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.map.hdb an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.map.logdb an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.map.qmsg an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.pre_map.cdb an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.pre_map.hdb an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.psp an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.pss an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.rtlv.hdb an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.rtlv_sg.cdb an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.rtlv_sg_swap.cdb an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.sgdiff.cdb an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.sgdiff.hdb an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.signalprobe.cdb an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.sld_design_entry_dsc.sci an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.syn_hier_info an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.tan.qmsg an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.tis_db_list.ddb an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.sld_design_entry.sci an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.eco.cdb an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\pwm_main.asm.rpt an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\pwm_main.cdf an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\pwm_main.done an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\pwm_main.dpf an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\pwm_main.fit.rpt an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\pwm_main.fit.smsg an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\pwm_main.fit.summary an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\pwm_main.flow.rpt an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\pwm_main.map.rpt an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\pwm_main.map.summary an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\pwm_main.pin an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\pwm_main.pof an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\pwm_main.qpf an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\pwm_main.qsf an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\pwm_main.tan.rpt an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\pwm_main.v an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\pwm_main_assignment_defaults.qdf an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\pwm_main.qws an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\testbench\test_pwm.v an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\altufm_osc0_altufm_osc_1p3 an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\clkgen an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\clk_gen an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\dutycycle an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\duty_cycle an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\pwm_gen an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\pwm_main an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\test_pwm an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\code an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\testbench an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example an501_design_example