文件名称:embedded_risc
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一个嵌入式RISC CPU 的Verilog 设计源码，可综合。内含详细的设计文挡。-an embedded RISC CPU design Verilog source code can be integrated. Detailed design containing the text block.
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压缩包 : 53607910embedded_risc.rar 列表 embedded_risc\CVS\Root embedded_risc\CVS\Repository embedded_risc\CVS\Template embedded_risc\CVS\Entries.Old embedded_risc\CVS\Entries embedded_risc\CVS\Entries.Extra.Old embedded_risc\CVS\Entries.Extra embedded_risc\CVS embedded_risc\SOC_Design.pdf embedded_risc\Machine_Language\CVS\Root embedded_risc\Machine_Language\CVS\Repository embedded_risc\Machine_Language\CVS\Template embedded_risc\Machine_Language\CVS\Entries.Old embedded_risc\Machine_Language\CVS\Entries embedded_risc\Machine_Language\CVS\Entries.Extra.Old embedded_risc\Machine_Language\CVS\Entries.Extra embedded_risc\Machine_Language\CVS embedded_risc\Machine_Language\program.txt embedded_risc\Machine_Language embedded_risc\Test_Bench_Verilog\CVS\Root embedded_risc\Test_Bench_Verilog\CVS\Repository embedded_risc\Test_Bench_Verilog\CVS\Template embedded_risc\Test_Bench_Verilog\CVS\Entries.Old embedded_risc\Test_Bench_Verilog\CVS\Entries embedded_risc\Test_Bench_Verilog\CVS\Entries.Extra.Old embedded_risc\Test_Bench_Verilog\CVS\Entries.Extra embedded_risc\Test_Bench_Verilog\CVS embedded_risc\Test_Bench_Verilog\Top_level_tb.tf embedded_risc\Test_Bench_Verilog embedded_risc\Verilog\CVS\Root embedded_risc\Verilog\CVS\Repository embedded_risc\Verilog\CVS\Template embedded_risc\Verilog\CVS\Entries.Old embedded_risc\Verilog\CVS\Entries embedded_risc\Verilog\CVS\Entries.Extra.Old embedded_risc\Verilog\CVS\Entries.Extra embedded_risc\Verilog\CVS embedded_risc\Verilog\ACC.V embedded_risc\Verilog\ALU.V embedded_risc\Verilog\CONTROL.V embedded_risc\Verilog\IR.V embedded_risc\Verilog\MEM.V embedded_risc\Verilog\MUX12.V embedded_risc\Verilog\MUX16.V embedded_risc\Verilog\PC.V embedded_risc\Verilog\bus_arbiter.v embedded_risc\Verilog\cmd_ack.v embedded_risc\Verilog\cmd_decoder.v embedded_risc\Verilog\cmd_detector.v embedded_risc\Verilog\cmd_generator.v embedded_risc\Verilog\cmd_internal_reg.v embedded_risc\Verilog\command_if.v embedded_risc\Verilog\data_cache_way0.v embedded_risc\Verilog\data_cache_way1.v embedded_risc\Verilog\data_cache_way2.v embedded_risc\Verilog\data_cache_way3.v embedded_risc\Verilog\data_in_reg.v embedded_risc\Verilog\data_port.v embedded_risc\Verilog\dma_cntrl.v embedded_risc\Verilog\dma_fifo.v embedded_risc\Verilog\dma_internal_reg.v embedded_risc\Verilog\flash_ctrl.v embedded_risc\Verilog\fsm.v embedded_risc\Verilog\instruction_cache_way0.v embedded_risc\Verilog\instruction_cache_way1.v embedded_risc\Verilog\instruction_cache_way2.v embedded_risc\Verilog\instruction_cache_way3.v embedded_risc\Verilog\k9f1g08u0m.v embedded_risc\Verilog\lru_data_cache.v embedded_risc\Verilog\lru_instruction_cache.v embedded_risc\Verilog\oe_generator.v embedded_risc\Verilog\parameter.v embedded_risc\Verilog\ras_cas_delay.v embedded_risc\Verilog\ref_ack.v embedded_risc\Verilog\ref_timer.v embedded_risc\Verilog\risc.v embedded_risc\Verilog\sdram.v embedded_risc\Verilog\sdram_cntrl.v embedded_risc\Verilog\sdram_mux.v embedded_risc\Verilog\sdram_port.v embedded_risc\Verilog\sdramctrl_rtl.v embedded_risc\Verilog\soc.v embedded_risc\Verilog\timer.v embedded_risc\Verilog\uart.v embedded_risc\Verilog embedded_risc