文件名称:PWM
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脉冲宽度调制，VHDL代码编写，包括QUARTUSII和MODELSIM工程以及testbench
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下载文件列表
压缩包 : 63535307pwm.rar 列表 脉冲宽度调制\an501.pdf 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\code\pwm_main.v 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\pulse_width_modulator.cr.mti 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\pulse_width_modulator.mpf 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\pwm_main.v 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\pwm_sim.cr.mti 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\pwm_sim.mpf 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\test_pwm.v 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\wave.bmp 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\wave.do 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\wave2.bmp 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\wave2.do 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\wave3.bmp 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\wave3.do 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\wave4.bmp 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\wave4.do 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\wave5.bmp 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\wave5.do 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\altufm_osc0_altufm_osc_1p3\verilog.asm 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\altufm_osc0_altufm_osc_1p3\_primary.dat 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\altufm_osc0_altufm_osc_1p3\_primary.vhd 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\clkgen\verilog.asm 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\clkgen\_primary.dat 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\clkgen\_primary.vhd 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\clk_gen\verilog.asm 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\clk_gen\_primary.dat 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\clk_gen\_primary.vhd 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\dutycycle\verilog.asm 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\dutycycle\_primary.dat 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\dutycycle\_primary.vhd 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\duty_cycle\verilog.asm 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\duty_cycle\_primary.dat 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\duty_cycle\_primary.vhd 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\pwm_gen\verilog.asm 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\pwm_gen\_primary.dat 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\pwm_gen\_primary.vhd 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\pwm_main\verilog.asm 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\pwm_main\_primary.dat 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\pwm_main\_primary.vhd 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\test_pwm\verilog.asm 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\test_pwm\_primary.dat 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\test_pwm\_primary.vhd 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\_info 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.(0).cnf.cdb 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.(0).cnf.hdb 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.(1).cnf.cdb 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.(1).cnf.hdb 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.(2).cnf.cdb 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.(2).cnf.hdb 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.(3).cnf.cdb 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.(3).cnf.hdb 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.(4).cnf.cdb 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.(4).cnf.hdb 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.asm.qmsg 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.asm_labs.ddb 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.cbx.xml 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.cmp.cdb 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.cmp.hdb 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.cmp.logdb 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.cmp.rdb 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.cmp.tdb 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.cmp0.ddb 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.dbp 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.db_info 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.eco.cdb 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.fit.qmsg 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.hier_info 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.hif 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.map.cdb 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.map.hdb 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.map.logdb 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.map.qmsg 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.pre_map.cdb 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.pre_map.hdb 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.psp 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.pss 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.rtlv.hdb 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.rtlv_sg.cdb 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.rtlv_sg_swap.cdb 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.sgdiff.cdb 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.sgdiff.hdb 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.signalprobe.cdb 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.sld_design_entry.sci 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.sld_design_entry_dsc.sci 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.syn_hier_info 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.tan.qmsg 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db\pwm_main.tis_db_list.ddb 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\pwm_main.asm.rpt 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\pwm_main.cdf 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\pwm_main.done 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\pwm_main.dpf 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\pwm_main.fit.rpt 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\pwm_main.fit.smsg 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\pwm_main.fit.summary 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\pwm_main.flow.rpt 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\pwm_main.map.rpt 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\pwm_main.map.summary 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\pwm_main.pin 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\pwm_main.pof 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\pwm_main.qpf 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\pwm_main.qsf 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\pwm_main.qws 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\pwm_main.tan.rpt 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\pwm_main.v 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\pwm_main_assignment_defaults.qdf 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\testbench\test_pwm.v 脉冲宽度调制\说明.txt 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\altufm_osc0_altufm_osc_1p3 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\clkgen 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\clk_gen 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\dutycycle 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\duty_cycle 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\pwm_gen 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\pwm_main 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work\test_pwm 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim\work 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus\db 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\code 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\modelsim 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\quartus 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\testbench 脉冲宽度调制\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example 脉冲宽度调制