文件名称:I2S
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这是一个I2S接口的VHDL实现源代码，I2S是一个通用的音频接口。-This is a I2S interface VHDL source code, I2S is a generic audio interface.
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下载文件列表
压缩包 : 11912894i2s.rar 列表 I2S\ca_rnd_vhd.txt I2S\clkgen_vhd.txt I2S\gen_vhd.txt I2S\i2s.files\i2s.html_img_240f4f4_4.gif I2S\i2s.files\input_timing.gif I2S\i2s.files\output_timing.gif I2S\i2s.files\typical_input.gif I2S\i2s.files I2S\i2s.htm I2S\i2s_dec_vhd.txt I2S\i2s_html240f4f4_3.txt I2S\OpenCores\i2s_interface\i2s_interface\bench\vhdl\tb_i2s.vhd I2S\OpenCores\i2s_interface\i2s_interface\bench\vhdl\wb_tb_pack.txt I2S\OpenCores\i2s_interface\i2s_interface\bench\vhdl I2S\OpenCores\i2s_interface\i2s_interface\bench I2S\OpenCores\i2s_interface\i2s_interface\doc\copying.txt I2S\OpenCores\i2s_interface\i2s_interface\doc\i2s.pdf I2S\OpenCores\i2s_interface\i2s_interface\doc\src\i2s.doc I2S\OpenCores\i2s_interface\i2s_interface\doc\src I2S\OpenCores\i2s_interface\i2s_interface\doc I2S\OpenCores\i2s_interface\i2s_interface\rtl\vhdl\dpram_rtl.txt I2S\OpenCores\i2s_interface\i2s_interface\rtl\vhdl\gen_control_reg.txt I2S\OpenCores\i2s_interface\i2s_interface\rtl\vhdl\gen_event_reg.txt I2S\OpenCores\i2s_interface\i2s_interface\rtl\vhdl\i2s_codec.vhd I2S\OpenCores\i2s_interface\i2s_interface\rtl\vhdl\i2s_version.vhd I2S\OpenCores\i2s_interface\i2s_interface\rtl\vhdl\rx_i2s_pack.vhd I2S\OpenCores\i2s_interface\i2s_interface\rtl\vhdl\rx_i2s_topm.vhd I2S\OpenCores\i2s_interface\i2s_interface\rtl\vhdl\rx_i2s_tops.vhd I2S\OpenCores\i2s_interface\i2s_interface\rtl\vhdl\rx_i2s_wbd.vhd I2S\OpenCores\i2s_interface\i2s_interface\rtl\vhdl\tx_i2s_pack.vhd I2S\OpenCores\i2s_interface\i2s_interface\rtl\vhdl\tx_i2s_topm.vhd I2S\OpenCores\i2s_interface\i2s_interface\rtl\vhdl\tx_i2s_tops.vhd I2S\OpenCores\i2s_interface\i2s_interface\rtl\vhdl\tx_i2s_wbd.vhd I2S\OpenCores\i2s_interface\i2s_interface\rtl\vhdl I2S\OpenCores\i2s_interface\i2s_interface\rtl I2S\OpenCores\i2s_interface\i2s_interface I2S\OpenCores\i2s_interface I2S\OpenCores\i2s_interface.tar.gz I2S\OpenCores\i2s_rel1_1\i2s_interface\bench\vhdl\tb_i2s.vhd I2S\OpenCores\i2s_rel1_1\i2s_interface\bench\vhdl\wb_tb_pack.txt I2S\OpenCores\i2s_rel1_1\i2s_interface\bench\vhdl\wb_tb_pack.vhd I2S\OpenCores\i2s_rel1_1\i2s_interface\bench\vhdl I2S\OpenCores\i2s_rel1_1\i2s_interface\bench I2S\OpenCores\i2s_rel1_1\i2s_interface\doc\copying.txt I2S\OpenCores\i2s_rel1_1\i2s_interface\doc\i2s.pdf I2S\OpenCores\i2s_rel1_1\i2s_interface\doc\src\i2s.doc I2S\OpenCores\i2s_rel1_1\i2s_interface\doc\src I2S\OpenCores\i2s_rel1_1\i2s_interface\doc I2S\OpenCores\i2s_rel1_1\i2s_interface\rtl\vhdl\dpram_altera.vhd I2S\OpenCores\i2s_rel1_1\i2s_interface\rtl\vhdl\dpram_rtl.txt I2S\OpenCores\i2s_rel1_1\i2s_interface\rtl\vhdl\dpram_rtl.vhd I2S\OpenCores\i2s_rel1_1\i2s_interface\rtl\vhdl\gen_control_reg.txt I2S\OpenCores\i2s_rel1_1\i2s_interface\rtl\vhdl\gen_control_reg.vhd I2S\OpenCores\i2s_rel1_1\i2s_interface\rtl\vhdl\gen_event_reg.txt I2S\OpenCores\i2s_rel1_1\i2s_interface\rtl\vhdl\gen_event_reg.vhd I2S\OpenCores\i2s_rel1_1\i2s_interface\rtl\vhdl\i2s_codec.vhd I2S\OpenCores\i2s_rel1_1\i2s_interface\rtl\vhdl\i2s_version.vhd I2S\OpenCores\i2s_rel1_1\i2s_interface\rtl\vhdl\rx_i2s_pack.vhd I2S\OpenCores\i2s_rel1_1\i2s_interface\rtl\vhdl\rx_i2s_topm.vhd I2S\OpenCores\i2s_rel1_1\i2s_interface\rtl\vhdl\rx_i2s_tops.vhd I2S\OpenCores\i2s_rel1_1\i2s_interface\rtl\vhdl\rx_i2s_wbd.vhd I2S\OpenCores\i2s_rel1_1\i2s_interface\rtl\vhdl\tx_i2s_pack.vhd I2S\OpenCores\i2s_rel1_1\i2s_interface\rtl\vhdl\tx_i2s_topm.vhd I2S\OpenCores\i2s_rel1_1\i2s_interface\rtl\vhdl\tx_i2s_tops.vhd I2S\OpenCores\i2s_rel1_1\i2s_interface\rtl\vhdl\tx_i2s_wbd.vhd I2S\OpenCores\i2s_rel1_1\i2s_interface\rtl\vhdl I2S\OpenCores\i2s_rel1_1\i2s_interface\rtl I2S\OpenCores\i2s_rel1_1\i2s_interface I2S\OpenCores\i2s_rel1_1 I2S\OpenCores\i2s_rel1_1.zip I2S\OpenCores\i2s_rel1_2\bench\CVS I2S\OpenCores\i2s_rel1_2\bench\vhdl\CVS I2S\OpenCores\i2s_rel1_2\bench\vhdl\tb_i2s.vhd I2S\OpenCores\i2s_rel1_2\bench\vhdl\tb_i2s.vhd~ I2S\OpenCores\i2s_rel1_2\bench\vhdl\wb_tb_pack.txt I2S\OpenCores\i2s_rel1_2\bench\vhdl\wb_tb_pack.vhd I2S\OpenCores\i2s_rel1_2\bench\vhdl I2S\OpenCores\i2s_rel1_2\bench I2S\OpenCores\i2s_rel1_2\doc\copying.txt I2S\OpenCores\i2s_rel1_2\doc\CVS I2S\OpenCores\i2s_rel1_2\doc\i2s.pdf I2S\OpenCores\i2s_rel1_2\doc\src\CVS I2S\OpenCores\i2s_rel1_2\doc\src\i2s.doc I2S\OpenCores\i2s_rel1_2\doc\src I2S\OpenCores\i2s_rel1_2\doc I2S\OpenCores\i2s_rel1_2\rtl\CVS I2S\OpenCores\i2s_rel1_2\rtl\vhdl\CVS I2S\OpenCores\i2s_rel1_2\rtl\vhdl\dpram_rtl.txt I2S\OpenCores\i2s_rel1_2\rtl\vhdl\dpram_rtl.vhd I2S\OpenCores\i2s_rel1_2\rtl\vhdl\gen_control_reg.txt I2S\OpenCores\i2s_rel1_2\rtl\vhdl\gen_control_reg.vhd I2S\OpenCores\i2s_rel1_2\rtl\vhdl\gen_event_reg.txt I2S\OpenCores\i2s_rel1_2\rtl\vhdl\gen_event_reg.vhd I2S\OpenCores\i2s_rel1_2\rtl\vhdl\i2s_codec.vhd I2S\OpenCores\i2s_rel1_2\rtl\vhdl\i2s_version.vhd I2S\OpenCores\i2s_rel1_2\rtl\vhdl\old I2S\OpenCores\i2s_rel1_2\rtl\vhdl\rx_i2s_pack.vhd I2S\OpenCores\i2s_rel1_2\rtl\vhdl\rx_i2s_topm.vhd I2S\OpenCores\i2s_rel1_2\rtl\vhdl\rx_i2s_tops.vhd I2S\OpenCores\i2s_rel1_2\rtl\vhdl\rx_i2s_wbd.vhd I2S\OpenCores\i2s_rel1_2\rtl\vhdl\tx_i2s_pack.vhd I2S\OpenCores\i2s_rel1_2\rtl\vhdl\tx_i2s_topm.vhd I2S\OpenCores\i2s_rel1_2\rtl\vhdl\tx_i2s_tops.vhd I2S\OpenCores\i2s_rel1_2\rtl\vhdl\tx_i2s_wbd.vhd I2S\OpenCores\i2s_rel1_2\rtl\vhdl I2S\OpenCores\i2s_rel1_2\rtl I2S\OpenCores\i2s_rel1_2 I2S\OpenCores\i2s_rel1_2.zip I2S\OpenCores I2S\rstgen_vhd.txt I2S