文件名称:sdram_all
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sdram 控制器的verilog 实现，包括用户逻辑和控制器的设计-SDRAM controller Verilog realization, including user logic and controller design
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下载文件列表
sdram_all
.........\db
.........\delay_reset
.........\...........\counter.bsf
.........\...........\counter.v
.........\...........\reset.bdf
.........\...........\reset.bsf
.........\pic
.........\pll
.........\...\pll_50.bsf
.........\...\pll_50.cmp
.........\...\pll_50.inc
.........\...\pll_50.ppf
.........\...\pll_50.v
.........\...\pll_50_bb.v
.........\...\pll_50_inst.v
.........\...\pll_50_waveforms.html
.........\source_sdram
.........\............\init_fsm.v
.........\............\main_fsm.v
.........\............\refresh.v
.........\............\sdram_top.bsf
.........\............\sdram_top.v
.........\............\sdr_par.v
.........\............\sdr_sig.v
.........\source_user
.........\...........\ram512.bsf
.........\...........\ram512.hex
.........\...........\ram512.mif
.........\...........\ram512.v
.........\...........\rom256.bsf
.........\...........\rom256.v
.........\...........\rom_value.hex
.........\...........\rom_value.mif
.........\...........\user_interface.bsf
.........\...........\user_interface.v
.........\...........\user_interface.v.bak
.........\testbench
.........\.........\singal.do
.........\.........\singal.do.bak
.........\.........\testbench.v
.........\.........\testbench.v.bak
.........\top.asm.rpt
.........\top.bdf
.........\top.done
.........\top.dpf
.........\top.eda.rpt
.........\top.fit.rpt
.........\top.fit.smsg
.........\top.fit.summary
.........\top.flow.rpt
.........\top.jdi
.........\top.map.rpt
.........\top.map.summary
.........\top.pin
.........\top.pof
.........\top.qpf
.........\top.qsf
.........\top.qws
.........\top.sof
.........\top.stp
.........\top.tan.rpt
.........\top.tan.summary
.........\top.v
.........\top_nativelink_simulation.rpt
.........\db
.........\delay_reset
.........\...........\counter.bsf
.........\...........\counter.v
.........\...........\reset.bdf
.........\...........\reset.bsf
.........\pic
.........\pll
.........\...\pll_50.bsf
.........\...\pll_50.cmp
.........\...\pll_50.inc
.........\...\pll_50.ppf
.........\...\pll_50.v
.........\...\pll_50_bb.v
.........\...\pll_50_inst.v
.........\...\pll_50_waveforms.html
.........\source_sdram
.........\............\init_fsm.v
.........\............\main_fsm.v
.........\............\refresh.v
.........\............\sdram_top.bsf
.........\............\sdram_top.v
.........\............\sdr_par.v
.........\............\sdr_sig.v
.........\source_user
.........\...........\ram512.bsf
.........\...........\ram512.hex
.........\...........\ram512.mif
.........\...........\ram512.v
.........\...........\rom256.bsf
.........\...........\rom256.v
.........\...........\rom_value.hex
.........\...........\rom_value.mif
.........\...........\user_interface.bsf
.........\...........\user_interface.v
.........\...........\user_interface.v.bak
.........\testbench
.........\.........\singal.do
.........\.........\singal.do.bak
.........\.........\testbench.v
.........\.........\testbench.v.bak
.........\top.asm.rpt
.........\top.bdf
.........\top.done
.........\top.dpf
.........\top.eda.rpt
.........\top.fit.rpt
.........\top.fit.smsg
.........\top.fit.summary
.........\top.flow.rpt
.........\top.jdi
.........\top.map.rpt
.........\top.map.summary
.........\top.pin
.........\top.pof
.........\top.qpf
.........\top.qsf
.........\top.qws
.........\top.sof
.........\top.stp
.........\top.tan.rpt
.........\top.tan.summary
.........\top.v
.........\top_nativelink_simulation.rpt