文件名称:mips_creative
- 所属分类：
- 微处理器(ARM/PowerPC等)
- 资源属性：
- [ASM] [源码]
- 上传时间：
- 2012-11-26
- 文件大小：
- 1.78mb
- 下载次数：
- 0次
- 提 供 者：
- 梁**
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
一个完整的MIPS CPU，创新设计，浙江大学某学生作品，有完整的说明文档、仿真文件和测试文件，可以直接综合和仿真。-a complete MIPS CPU, innovative design, a student of Zhejiang University works with complete documentation, simulation and test documents, and can be directly integrated simulation.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
MIPS
....\ISE
....\...\.untf
....\...\automake.log
....\...\global.xpi
....\...\global_map.ncd
....\...\global_map.ngm
....\...\global_pad.csv
....\...\global_pad.txt
....\...\global_vhdl.prj
....\...\ISE.dhp
....\...\ISE.npl
....\...\main.bld
....\...\main.cmd_log
....\...\main.lso
....\...\main.mrp
....\...\main.nc1
....\...\main.ncd
....\...\main.ngc
....\...\main.ngd
....\...\main.ngm
....\...\main.ngr
....\...\main.pad
....\...\main.pad_txt
....\...\main.par
....\...\main.par_nlf
....\...\main.pcf
....\...\main.placed_ncd_tracker
....\...\main.prj
....\...\main.routed_ncd_tracker
....\...\main.stx
....\...\main.syr
....\...\main.twr
....\...\main.twx
....\...\main.versim_par
....\...\main.xpi
....\...\main_map.ncd
....\...\main_map.ngm
....\...\main_pad.csv
....\...\main_pad.txt
....\...\main_TEST_v_tf.tdo
....\...\main_TEST_v_tf.udo
....\...\main_timesim.nlf
....\...\main_timesim.sdf
....\...\main_timesim.v
....\...\main_vhdl.prj
....\...\TEST.v
....\...\transcript
....\...\vsim.wlf
....\...\work
....\...\....\_info
....\...\xst
....\...\...\work
....\...\...\....\hdllib.ref
....\...\...\....\vlg0A
....\...\...\....\.....\Data_Memory.bin
....\...\...\....\vlg15
....\...\...\....\.....\global.bin
....\...\...\....\vlg20
....\...\...\....\.....\Registers.bin
....\...\...\....\vlg2D
....\...\...\....\.....\main.bin
....\...\...\....\vlg30
....\...\...\....\.....\Decode.bin
....\...\...\....\vlg3B
....\...\...\....\.....\Code_Memory.bin
....\...\...\....\vlg41
....\...\...\....\.....\Control.bin
....\...\...\....\vlg47
....\...\...\....\.....\Execute.bin
....\...\...\....\vlg62
....\...\...\....\.....\Fetch.bin
....\...\_ngo
....\...\....\netlist.lst
....\...\__projnav
....\...\.........\coregen.rsp
....\...\.........\createTF.err
....\...\.........\ednTOngd_tcl.rsp
....\...\.........\global.xst
....\...\.........\ISE.gfl
....\...\.........\ISE_flowplus.gfl
....\...\.........\main.xst
....\...\.........\map.log
....\...\.........\nc1TOncd_tcl.rsp
....\...\.........\netgen_par_tcl.rsp
....\...\.........\par.log
....\...\.........\posttrc.log
....\...\.........\runXst_tcl.rsp
....\...\__projnav.log
....\mips.doc
....\ModelSim
....\........\MIPS.cr.mti
....\........\MIPS.mpf
....\........\work
....\........\....\@code_@memory
....\........\....\.............\verilog.asm
....\........\....\.............\_primary.dat
....\........\....\.............\_primary.vhd
....\........\....\@control
....\........\....\........\verilog.asm
....\ISE
....\...\.untf
....\...\automake.log
....\...\global.xpi
....\...\global_map.ncd
....\...\global_map.ngm
....\...\global_pad.csv
....\...\global_pad.txt
....\...\global_vhdl.prj
....\...\ISE.dhp
....\...\ISE.npl
....\...\main.bld
....\...\main.cmd_log
....\...\main.lso
....\...\main.mrp
....\...\main.nc1
....\...\main.ncd
....\...\main.ngc
....\...\main.ngd
....\...\main.ngm
....\...\main.ngr
....\...\main.pad
....\...\main.pad_txt
....\...\main.par
....\...\main.par_nlf
....\...\main.pcf
....\...\main.placed_ncd_tracker
....\...\main.prj
....\...\main.routed_ncd_tracker
....\...\main.stx
....\...\main.syr
....\...\main.twr
....\...\main.twx
....\...\main.versim_par
....\...\main.xpi
....\...\main_map.ncd
....\...\main_map.ngm
....\...\main_pad.csv
....\...\main_pad.txt
....\...\main_TEST_v_tf.tdo
....\...\main_TEST_v_tf.udo
....\...\main_timesim.nlf
....\...\main_timesim.sdf
....\...\main_timesim.v
....\...\main_vhdl.prj
....\...\TEST.v
....\...\transcript
....\...\vsim.wlf
....\...\work
....\...\....\_info
....\...\xst
....\...\...\work
....\...\...\....\hdllib.ref
....\...\...\....\vlg0A
....\...\...\....\.....\Data_Memory.bin
....\...\...\....\vlg15
....\...\...\....\.....\global.bin
....\...\...\....\vlg20
....\...\...\....\.....\Registers.bin
....\...\...\....\vlg2D
....\...\...\....\.....\main.bin
....\...\...\....\vlg30
....\...\...\....\.....\Decode.bin
....\...\...\....\vlg3B
....\...\...\....\.....\Code_Memory.bin
....\...\...\....\vlg41
....\...\...\....\.....\Control.bin
....\...\...\....\vlg47
....\...\...\....\.....\Execute.bin
....\...\...\....\vlg62
....\...\...\....\.....\Fetch.bin
....\...\_ngo
....\...\....\netlist.lst
....\...\__projnav
....\...\.........\coregen.rsp
....\...\.........\createTF.err
....\...\.........\ednTOngd_tcl.rsp
....\...\.........\global.xst
....\...\.........\ISE.gfl
....\...\.........\ISE_flowplus.gfl
....\...\.........\main.xst
....\...\.........\map.log
....\...\.........\nc1TOncd_tcl.rsp
....\...\.........\netgen_par_tcl.rsp
....\...\.........\par.log
....\...\.........\posttrc.log
....\...\.........\runXst_tcl.rsp
....\...\__projnav.log
....\mips.doc
....\ModelSim
....\........\MIPS.cr.mti
....\........\MIPS.mpf
....\........\work
....\........\....\@code_@memory
....\........\....\.............\verilog.asm
....\........\....\.............\_primary.dat
....\........\....\.............\_primary.vhd
....\........\....\@control
....\........\....\........\verilog.asm