文件名称:FIFO_Buffer
- 所属分类：
- 微处理器(ARM/PowerPC等)
- 资源属性：
- [ASM] [源码]
- 上传时间：
- 2012-11-26
- 文件大小：
- 68kb
- 下载次数：
- 0次
- 提 供 者：
- 张**
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
同步及异步时序电路fifo源程序及其测试程序.rar - fifo源程序，erilog编写~具有较强的参考价值~ -Synchronous and asynchronous sequential circuits fifo source and test procedures. Rar- fifo source, erilog prepared ~ has a strong reference to the value of ~
(系统自动生成,下载前可以参看下载内容)
下载文件列表
FIFO_Asyn
.........\FIFO_Buffer.v
.........\FIFO_Buffer.v.bak
.........\my_FIFO_Asyn.cr.mti
.........\my_FIFO_Asyn.mpf
.........\Ser_Par_Conv_32.v
.........\t_FIFO_Clock_Domain_Synch.v
.........\t_FIFO_Clock_Domain_Synch.v.bak
.........\vsim.wlf
.........\work
.........\....\@f@i@f@o_@buffer
.........\....\................\verilog.asm
.........\....\................\_primary.dat
.........\....\................\_primary.vhd
.........\....\@ser_@par_@conv_32
.........\....\..................\verilog.asm
.........\....\..................\_primary.dat
.........\....\..................\_primary.vhd
.........\....\t_@f@i@f@o_@clock_@domain_@synch
.........\....\................................\verilog.asm
.........\....\................................\_primary.dat
.........\....\................................\_primary.vhd
.........\....\write_synchronizer
.........\....\..................\verilog.asm
.........\....\..................\_primary.dat
.........\....\..................\_primary.vhd
.........\....\_info
.........\write_synchronizer.v
FIFO_Syn
........\FIFO_Buffer.v
........\FIFO_Syn.cr.mti
........\FIFO_Syn.mpf
........\t_FIFO_Buffer.v
........\vsim.wlf
........\work
........\....\@f@i@f@o_@buffer
........\....\................\verilog.asm
........\....\................\_primary.dat
........\....\................\_primary.vhd
........\....\t_@f@i@f@o_@buffer
........\....\..................\verilog.asm
........\....\..................\_primary.dat
........\....\..................\_primary.vhd
........\....\_info
.........\FIFO_Buffer.v
.........\FIFO_Buffer.v.bak
.........\my_FIFO_Asyn.cr.mti
.........\my_FIFO_Asyn.mpf
.........\Ser_Par_Conv_32.v
.........\t_FIFO_Clock_Domain_Synch.v
.........\t_FIFO_Clock_Domain_Synch.v.bak
.........\vsim.wlf
.........\work
.........\....\@f@i@f@o_@buffer
.........\....\................\verilog.asm
.........\....\................\_primary.dat
.........\....\................\_primary.vhd
.........\....\@ser_@par_@conv_32
.........\....\..................\verilog.asm
.........\....\..................\_primary.dat
.........\....\..................\_primary.vhd
.........\....\t_@f@i@f@o_@clock_@domain_@synch
.........\....\................................\verilog.asm
.........\....\................................\_primary.dat
.........\....\................................\_primary.vhd
.........\....\write_synchronizer
.........\....\..................\verilog.asm
.........\....\..................\_primary.dat
.........\....\..................\_primary.vhd
.........\....\_info
.........\write_synchronizer.v
FIFO_Syn
........\FIFO_Buffer.v
........\FIFO_Syn.cr.mti
........\FIFO_Syn.mpf
........\t_FIFO_Buffer.v
........\vsim.wlf
........\work
........\....\@f@i@f@o_@buffer
........\....\................\verilog.asm
........\....\................\_primary.dat
........\....\................\_primary.vhd
........\....\t_@f@i@f@o_@buffer
........\....\..................\verilog.asm
........\....\..................\_primary.dat
........\....\..................\_primary.vhd
........\....\_info