文件名称:Example-b8-1
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使用ModelSim对Altera设计进行功能仿真
对于没有使用到Altera的MegaWizard或LPM的设计而言，功能仿真比较简单，读者只需依据8.2.5小节描述的步骤依次执行即可，对于使用了MegaWizard或LPM的设计，则必需在仿真时指定相关的Altera库-Altera use ModelSim for functional simulation for designs that do not use Altera
对于没有使用到Altera的MegaWizard或LPM的设计而言，功能仿真比较简单，读者只需依据8.2.5小节描述的步骤依次执行即可，对于使用了MegaWizard或LPM的设计，则必需在仿真时指定相关的Altera库-Altera use ModelSim for functional simulation for designs that do not use Altera
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下载文件列表
Altera_lib_files
................\220model.txt
................\220model.v
................\220model.vhd
................\220model_87.vhd
................\220pack.vhd
................\altera_mf.txt
................\altera_mf.v
................\altera_mf.vhd
................\altera_mf_87.vhd
................\altera_mf_components.vhd
................\stratix_atoms.v
................\stratix_atoms.vhd
................\stratix_components.vhd
func_sim
........\dpram8x32.v
........\func_sim.cr.mti
........\func_sim.mpf
........\func_sim_wave.wlf
........\pllx2.v
........\pll_ram.v
........\pll_ram_tb.v
........\transcript
........\vsim.wlf
........\wave.do
........\work
........\....\dpram8x32
........\....\.........\verilog.asm
........\....\.........\_primary.dat
........\....\.........\_primary.vhd
........\....\pllx2
........\....\.....\verilog.asm
........\....\.....\_primary.dat
........\....\.....\_primary.vhd
........\....\pll_ram
........\....\.......\verilog.asm
........\....\.......\_primary.dat
........\....\.......\_primary.vhd
........\....\pll_ram_tb
........\....\..........\verilog.asm
........\....\..........\_primary.dat
........\....\..........\_primary.vhd
........\....\_info
pll_ram
.......\cmp_state.ini
.......\db
.......\..\altsyncram_7bc1.tdf
.......\..\pll_ram.asm.qmsg
.......\..\pll_ram.cmp.cdb
.......\..\pll_ram.cmp.ddb
.......\..\pll_ram.cmp.hdb
.......\..\pll_ram.cmp.rdb
.......\..\pll_ram.cmp.tdb
.......\..\pll_ram.csf.qmsg
.......\..\pll_ram.db_info
.......\..\pll_ram.eda.qmsg
.......\..\pll_ram.fit.qmsg
.......\..\pll_ram.hif
.......\..\pll_ram.icc
.......\..\pll_ram.map.cdb
.......\..\pll_ram.map.hdb
.......\..\pll_ram.map.qmsg
.......\..\pll_ram.pll_ram.sld_design_entry.sci
.......\..\pll_ram.pre_map.hdb
.......\..\pll_ram.project.hdb
.......\..\pll_ram.rtlv.hdb
.......\..\pll_ram.rtlv_sg.cdb
.......\..\pll_ram.rtlv_sg_swap.cdb
.......\..\pll_ram.sgdiff.cdb
.......\..\pll_ram.sgdiff.hdb
.......\..\pll_ram.signalprobe.cdb
.......\..\pll_ram.tan.qmsg
.......\..\pll_ram_cmp.qrpt
.......\..\pll_ram_hier_info
.......\..\pll_ram_syn_hier_info
.......\dpram8x32.v
.......\pllx2.v
.......\pll_ram.asm.rpt
.......\pll_ram.done
.......\pll_ram.eda.rpt
.......\pll_ram.fit.eqn
.......\pll_ram.fit.rpt
.......\pll_ram.flow.rpt
.......\pll_ram.map.eqn
.......\pll_ram.map.rpt
.......\pll_ram.pin
.......\pll_ram.pof
.......\pll_ram.qpf
.......\pll_ram.qsf
.......\pll_ram.qws
.......\pll_ram.sof
.......\pll_ram.tan.rpt
.......\pll_ram.tan.summary
.......\pll_ram.v
.......\simulation
.......\..........\modelsim
.......\..........\........\pll_ram.vo
.......\..........\........\pll_ram_modelsim.xrf
.......\..........\........\pll_ram_v.sdo
................\220model.txt
................\220model.v
................\220model.vhd
................\220model_87.vhd
................\220pack.vhd
................\altera_mf.txt
................\altera_mf.v
................\altera_mf.vhd
................\altera_mf_87.vhd
................\altera_mf_components.vhd
................\stratix_atoms.v
................\stratix_atoms.vhd
................\stratix_components.vhd
func_sim
........\dpram8x32.v
........\func_sim.cr.mti
........\func_sim.mpf
........\func_sim_wave.wlf
........\pllx2.v
........\pll_ram.v
........\pll_ram_tb.v
........\transcript
........\vsim.wlf
........\wave.do
........\work
........\....\dpram8x32
........\....\.........\verilog.asm
........\....\.........\_primary.dat
........\....\.........\_primary.vhd
........\....\pllx2
........\....\.....\verilog.asm
........\....\.....\_primary.dat
........\....\.....\_primary.vhd
........\....\pll_ram
........\....\.......\verilog.asm
........\....\.......\_primary.dat
........\....\.......\_primary.vhd
........\....\pll_ram_tb
........\....\..........\verilog.asm
........\....\..........\_primary.dat
........\....\..........\_primary.vhd
........\....\_info
pll_ram
.......\cmp_state.ini
.......\db
.......\..\altsyncram_7bc1.tdf
.......\..\pll_ram.asm.qmsg
.......\..\pll_ram.cmp.cdb
.......\..\pll_ram.cmp.ddb
.......\..\pll_ram.cmp.hdb
.......\..\pll_ram.cmp.rdb
.......\..\pll_ram.cmp.tdb
.......\..\pll_ram.csf.qmsg
.......\..\pll_ram.db_info
.......\..\pll_ram.eda.qmsg
.......\..\pll_ram.fit.qmsg
.......\..\pll_ram.hif
.......\..\pll_ram.icc
.......\..\pll_ram.map.cdb
.......\..\pll_ram.map.hdb
.......\..\pll_ram.map.qmsg
.......\..\pll_ram.pll_ram.sld_design_entry.sci
.......\..\pll_ram.pre_map.hdb
.......\..\pll_ram.project.hdb
.......\..\pll_ram.rtlv.hdb
.......\..\pll_ram.rtlv_sg.cdb
.......\..\pll_ram.rtlv_sg_swap.cdb
.......\..\pll_ram.sgdiff.cdb
.......\..\pll_ram.sgdiff.hdb
.......\..\pll_ram.signalprobe.cdb
.......\..\pll_ram.tan.qmsg
.......\..\pll_ram_cmp.qrpt
.......\..\pll_ram_hier_info
.......\..\pll_ram_syn_hier_info
.......\dpram8x32.v
.......\pllx2.v
.......\pll_ram.asm.rpt
.......\pll_ram.done
.......\pll_ram.eda.rpt
.......\pll_ram.fit.eqn
.......\pll_ram.fit.rpt
.......\pll_ram.flow.rpt
.......\pll_ram.map.eqn
.......\pll_ram.map.rpt
.......\pll_ram.pin
.......\pll_ram.pof
.......\pll_ram.qpf
.......\pll_ram.qsf
.......\pll_ram.qws
.......\pll_ram.sof
.......\pll_ram.tan.rpt
.......\pll_ram.tan.summary
.......\pll_ram.v
.......\simulation
.......\..........\modelsim
.......\..........\........\pll_ram.vo
.......\..........\........\pll_ram_modelsim.xrf
.......\..........\........\pll_ram_v.sdo