文件名称:S6_VGA_change
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verilog源代码，quartusII工程。程序实现VGA时序。控制VGA显示器输出图形。在quartusII中客直接运行，-Verilog source code, quartusII works. Procedures to achieve VGA timing. VGA graphics display control output. QuartusII in the direct run-off,
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VGA
VGA时序
vga显示
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UART
quartus
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S6_VGA_change
rar
quartus
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UART
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S6_VGA_change
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FPGA
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VGA
timing
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S6_VGA_change
.............\Doc
.............\...\程序说明.txt
.............\Proj
.............\....\cmp_state.ini
.............\....\ColorBar.asm.rpt
.............\....\ColorBar.cdf
.............\....\ColorBar.done
.............\....\ColorBar.eda.rpt
.............\....\ColorBar.fit.eqn
.............\....\ColorBar.fit.rpt
.............\....\ColorBar.fit.summary
.............\....\ColorBar.flow.rpt
.............\....\ColorBar.map.eqn
.............\....\ColorBar.map.rpt
.............\....\ColorBar.map.summary
.............\....\ColorBar.mif
.............\....\ColorBar.pin
.............\....\ColorBar.pof
.............\....\ColorBar.qpf
.............\....\ColorBar.qsf
.............\....\ColorBar.qws
.............\....\ColorBar.sof
.............\....\ColorBar.tan.rpt
.............\....\ColorBar.tan.summary
.............\....\ColorBar_assignment_defaults.qdf
.............\....\db
.............\....\..\altsyncram_1f92.tdf
.............\....\..\altsyncram_fl82.tdf
.............\....\..\altsyncram_hl82.tdf
.............\....\..\cntr_f29.tdf
.............\....\..\cntr_gq7.tdf
.............\....\..\cntr_ln7.tdf
.............\....\..\cntr_no8.tdf
.............\....\..\cntr_qt7.tdf
.............\....\..\cntr_rt7.tdf
.............\....\..\cntr_vt9.tdf
.............\....\..\ColorBar.asm.qmsg
.............\....\..\ColorBar.cbx.xml
.............\....\..\ColorBar.cmp.rdb
.............\....\..\ColorBar.db_info
.............\....\..\ColorBar.eco.cdb
.............\....\..\ColorBar.eda.qmsg
.............\....\..\ColorBar.fit.qmsg
.............\....\..\ColorBar.hier_info
.............\....\..\ColorBar.hif
.............\....\..\ColorBar.map.cdb
.............\....\..\ColorBar.map.hdb
.............\....\..\ColorBar.map.qmsg
.............\....\..\ColorBar.pre_map.cdb
.............\....\..\ColorBar.pre_map.hdb
.............\....\..\ColorBar.psp
.............\....\..\ColorBar.rtlv.hdb
.............\....\..\ColorBar.rtlv_sg.cdb
.............\....\..\ColorBar.rtlv_sg_swap.cdb
.............\....\..\ColorBar.sgdiff.cdb
.............\....\..\ColorBar.sgdiff.hdb
.............\....\..\ColorBar.sld_design_entry.sci
.............\....\..\ColorBar.sld_design_entry_dsc.sci
.............\....\..\ColorBar.syn_hier_info
.............\....\..\ColorBar.tan.qmsg
.............\....\..\ColorBar_cmp.qrpt
.............\....\..\decode_9ie.tdf
.............\....\rom.bsf
.............\....\rom.v
.............\....\rom_8.bsf
.............\....\rom_8.v
.............\....\rom_8_bb.v
.............\....\rom_bb.v
.............\....\simulation
.............\....\..........\modelsim
.............\....\..........\........\ColorBar.vo
.............\....\..........\........\ColorBar_modelsim.xrf
.............\....\..........\........\ColorBar_v.sdo
.............\....\..........\........\cyclone_atoms.v
.............\....\..........\........\vga_test.cr.mti
.............\....\..........\........\vga_test.mpf
.............\....\..........\........\vga_test.v
.............\....\..........\........\vga_vl.v
.............\....\..........\........\vsim.wlf
.............\....\..........\........\wave.do
.............\....\..........\........\work
.............\....\..........\........\....\@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e
.............\....\..........\........\....\................................\verilog.asm
.............\....\..........\........\....\................................\_primary.dat
.............\....\..........\........\....\................................\_primary.vhd
.............\....\..........\........\....\@color@bar
.............\....\..........\........\....\..........\verilog.asm
.............\....\..........\........\....\..........\_primary.dat
.............\....\..........\........\....\..........\_primary.vhd
.............\....\..........\........\....\cyclone_and1
.............\....\..........\........\....\............\verilog.asm
.............\....\..........\........\....\............\_primary.dat
.............\....\..........\........\....\............\_primary.vhd
.............\....\..........\........\....\cyclone_and16
.............\....\..........\....
.............\Doc
.............\...\程序说明.txt
.............\Proj
.............\....\cmp_state.ini
.............\....\ColorBar.asm.rpt
.............\....\ColorBar.cdf
.............\....\ColorBar.done
.............\....\ColorBar.eda.rpt
.............\....\ColorBar.fit.eqn
.............\....\ColorBar.fit.rpt
.............\....\ColorBar.fit.summary
.............\....\ColorBar.flow.rpt
.............\....\ColorBar.map.eqn
.............\....\ColorBar.map.rpt
.............\....\ColorBar.map.summary
.............\....\ColorBar.mif
.............\....\ColorBar.pin
.............\....\ColorBar.pof
.............\....\ColorBar.qpf
.............\....\ColorBar.qsf
.............\....\ColorBar.qws
.............\....\ColorBar.sof
.............\....\ColorBar.tan.rpt
.............\....\ColorBar.tan.summary
.............\....\ColorBar_assignment_defaults.qdf
.............\....\db
.............\....\..\altsyncram_1f92.tdf
.............\....\..\altsyncram_fl82.tdf
.............\....\..\altsyncram_hl82.tdf
.............\....\..\cntr_f29.tdf
.............\....\..\cntr_gq7.tdf
.............\....\..\cntr_ln7.tdf
.............\....\..\cntr_no8.tdf
.............\....\..\cntr_qt7.tdf
.............\....\..\cntr_rt7.tdf
.............\....\..\cntr_vt9.tdf
.............\....\..\ColorBar.asm.qmsg
.............\....\..\ColorBar.cbx.xml
.............\....\..\ColorBar.cmp.rdb
.............\....\..\ColorBar.db_info
.............\....\..\ColorBar.eco.cdb
.............\....\..\ColorBar.eda.qmsg
.............\....\..\ColorBar.fit.qmsg
.............\....\..\ColorBar.hier_info
.............\....\..\ColorBar.hif
.............\....\..\ColorBar.map.cdb
.............\....\..\ColorBar.map.hdb
.............\....\..\ColorBar.map.qmsg
.............\....\..\ColorBar.pre_map.cdb
.............\....\..\ColorBar.pre_map.hdb
.............\....\..\ColorBar.psp
.............\....\..\ColorBar.rtlv.hdb
.............\....\..\ColorBar.rtlv_sg.cdb
.............\....\..\ColorBar.rtlv_sg_swap.cdb
.............\....\..\ColorBar.sgdiff.cdb
.............\....\..\ColorBar.sgdiff.hdb
.............\....\..\ColorBar.sld_design_entry.sci
.............\....\..\ColorBar.sld_design_entry_dsc.sci
.............\....\..\ColorBar.syn_hier_info
.............\....\..\ColorBar.tan.qmsg
.............\....\..\ColorBar_cmp.qrpt
.............\....\..\decode_9ie.tdf
.............\....\rom.bsf
.............\....\rom.v
.............\....\rom_8.bsf
.............\....\rom_8.v
.............\....\rom_8_bb.v
.............\....\rom_bb.v
.............\....\simulation
.............\....\..........\modelsim
.............\....\..........\........\ColorBar.vo
.............\....\..........\........\ColorBar_modelsim.xrf
.............\....\..........\........\ColorBar_v.sdo
.............\....\..........\........\cyclone_atoms.v
.............\....\..........\........\vga_test.cr.mti
.............\....\..........\........\vga_test.mpf
.............\....\..........\........\vga_test.v
.............\....\..........\........\vga_vl.v
.............\....\..........\........\vsim.wlf
.............\....\..........\........\wave.do
.............\....\..........\........\work
.............\....\..........\........\....\@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e
.............\....\..........\........\....\................................\verilog.asm
.............\....\..........\........\....\................................\_primary.dat
.............\....\..........\........\....\................................\_primary.vhd
.............\....\..........\........\....\@color@bar
.............\....\..........\........\....\..........\verilog.asm
.............\....\..........\........\....\..........\_primary.dat
.............\....\..........\........\....\..........\_primary.vhd
.............\....\..........\........\....\cyclone_and1
.............\....\..........\........\....\............\verilog.asm
.............\....\..........\........\....\............\_primary.dat
.............\....\..........\........\....\............\_primary.vhd
.............\....\..........\........\....\cyclone_and16
.............\....\..........\....