文件名称:uart_verilog
- 所属分类：
- 微处理器(ARM/PowerPC等)
- 资源属性：
- [ASM] [源码]
- 上传时间：
- 2012-11-26
- 文件大小：
- 1.76mb
- 下载次数：
- 0次
- 提 供 者：
- 王*
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
this is a sample about UART transmission,it s default installation is D:\RedLogic\RCII_samples, and the software environment is quatrusII 5.0,it is usefull for studying UART.-this is a sample about UART transmission, it s default installation is D: RedLogicRCII_samples, and the software environment is quatrusII 5.0, it is usefull for studying UART.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
UART
....\Doc
....\...\RCA-CY1C12开发板UART示例说明.doc
....\...\sscom.ini
....\...\sscom32.exe
....\...\xapp341.pdf
....\func_sim
....\........\transcript
....\........\txmit_tf.do
....\........\uart.cr.mti
....\........\uart.mpf
....\........\uart_tb.do
....\........\uart_tb_fixed.do
....\........\vish_stacktrace.vstf
....\........\vsim.wlf
....\........\wave.do
....\........\work
....\........\....\@u@a@r@t_tb
....\........\....\...........\verilog.asm
....\........\....\...........\_primary.dat
....\........\....\...........\_primary.vhd
....\........\....\rcvr
....\........\....\....\verilog.asm
....\........\....\....\_primary.dat
....\........\....\....\_primary.vhd
....\........\....\txmit
....\........\....\.....\verilog.asm
....\........\....\.....\_primary.dat
....\........\....\.....\_primary.vhd
....\........\....\uart
....\........\....\....\verilog.asm
....\........\....\....\_primary.dat
....\........\....\....\_primary.vhd
....\........\....\uart_if
....\........\....\.......\verilog.asm
....\........\....\.......\_primary.dat
....\........\....\.......\_primary.vhd
....\........\....\_info
....\physical
....\........\altclklock0.bsf
....\........\altclklock0.v
....\........\altclklock0_bb.v
....\........\async_transmitter.bsf
....\........\cmp_state.ini
....\........\db
....\........\..\altsyncram_8tj.tdf
....\........\..\altsyncram_9un.tdf
....\........\..\altsyncram_g5q.tdf
....\........\..\cntr_cs6.tdf
....\........\..\cntr_gs6.tdf
....\........\..\cntr_ub7.tdf
....\........\..\cntr_vt6.tdf
....\........\..\uart_if.asm.qmsg
....\........\..\uart_if.cbx.xml
....\........\..\uart_if.cmp.cdb
....\........\..\uart_if.cmp.hdb
....\........\..\uart_if.cmp.rdb
....\........\..\uart_if.cmp.tdb
....\........\..\uart_if.cmp0.ddb
....\........\..\uart_if.db_info
....\........\..\uart_if.eco.cdb
....\........\..\uart_if.eda.qmsg
....\........\..\uart_if.fit.qmsg
....\........\..\uart_if.hier_info
....\........\..\uart_if.hif
....\........\..\uart_if.map.cdb
....\........\..\uart_if.map.hdb
....\........\..\uart_if.map.qmsg
....\........\..\uart_if.pre_map.cdb
....\........\..\uart_if.pre_map.hdb
....\........\..\uart_if.psp
....\........\..\uart_if.rtlv.hdb
....\........\..\uart_if.rtlv_sg.cdb
....\........\..\uart_if.rtlv_sg_swap.cdb
....\........\..\uart_if.sgdiff.cdb
....\........\..\uart_if.sgdiff.hdb
....\........\..\uart_if.signalprobe.cdb
....\........\..\uart_if.sld_design_entry.sci
....\........\..\uart_if.sld_design_entry_dsc.sci
....\........\..\uart_if.syn_hier_info
....\........\..\uart_if.tan.qmsg
....\........\..\uart_if_cmp.qrpt
....\........\..\uart_if_hier_info
....\........\..\uart_if_syn_hier_info
....\........\div.bsf
....\........\div_2.bsf
....\........\div_2.v
....\........\filter.bsf
....\........\LED_flush.bsf
....\........\quartus_nativelink_simulation.log
....\........\rcvr.bsf
....\........\simulation
....\........\..........\modelsim
....\........\..........\........\cyclone_atoms.v
....\........\..........\........\modelsim.ini
....\........\..........\........\modelsim_work
....\........\..........\........\.............\@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e
....\........\..........\........\.............\................................\verilog.asm
....\........\..........\........\.............\................................\_primary.dat
....\........\..........\........\.............\................................\_primary.vhd
....\Doc
....\...\RCA-CY1C12开发板UART示例说明.doc
....\...\sscom.ini
....\...\sscom32.exe
....\...\xapp341.pdf
....\func_sim
....\........\transcript
....\........\txmit_tf.do
....\........\uart.cr.mti
....\........\uart.mpf
....\........\uart_tb.do
....\........\uart_tb_fixed.do
....\........\vish_stacktrace.vstf
....\........\vsim.wlf
....\........\wave.do
....\........\work
....\........\....\@u@a@r@t_tb
....\........\....\...........\verilog.asm
....\........\....\...........\_primary.dat
....\........\....\...........\_primary.vhd
....\........\....\rcvr
....\........\....\....\verilog.asm
....\........\....\....\_primary.dat
....\........\....\....\_primary.vhd
....\........\....\txmit
....\........\....\.....\verilog.asm
....\........\....\.....\_primary.dat
....\........\....\.....\_primary.vhd
....\........\....\uart
....\........\....\....\verilog.asm
....\........\....\....\_primary.dat
....\........\....\....\_primary.vhd
....\........\....\uart_if
....\........\....\.......\verilog.asm
....\........\....\.......\_primary.dat
....\........\....\.......\_primary.vhd
....\........\....\_info
....\physical
....\........\altclklock0.bsf
....\........\altclklock0.v
....\........\altclklock0_bb.v
....\........\async_transmitter.bsf
....\........\cmp_state.ini
....\........\db
....\........\..\altsyncram_8tj.tdf
....\........\..\altsyncram_9un.tdf
....\........\..\altsyncram_g5q.tdf
....\........\..\cntr_cs6.tdf
....\........\..\cntr_gs6.tdf
....\........\..\cntr_ub7.tdf
....\........\..\cntr_vt6.tdf
....\........\..\uart_if.asm.qmsg
....\........\..\uart_if.cbx.xml
....\........\..\uart_if.cmp.cdb
....\........\..\uart_if.cmp.hdb
....\........\..\uart_if.cmp.rdb
....\........\..\uart_if.cmp.tdb
....\........\..\uart_if.cmp0.ddb
....\........\..\uart_if.db_info
....\........\..\uart_if.eco.cdb
....\........\..\uart_if.eda.qmsg
....\........\..\uart_if.fit.qmsg
....\........\..\uart_if.hier_info
....\........\..\uart_if.hif
....\........\..\uart_if.map.cdb
....\........\..\uart_if.map.hdb
....\........\..\uart_if.map.qmsg
....\........\..\uart_if.pre_map.cdb
....\........\..\uart_if.pre_map.hdb
....\........\..\uart_if.psp
....\........\..\uart_if.rtlv.hdb
....\........\..\uart_if.rtlv_sg.cdb
....\........\..\uart_if.rtlv_sg_swap.cdb
....\........\..\uart_if.sgdiff.cdb
....\........\..\uart_if.sgdiff.hdb
....\........\..\uart_if.signalprobe.cdb
....\........\..\uart_if.sld_design_entry.sci
....\........\..\uart_if.sld_design_entry_dsc.sci
....\........\..\uart_if.syn_hier_info
....\........\..\uart_if.tan.qmsg
....\........\..\uart_if_cmp.qrpt
....\........\..\uart_if_hier_info
....\........\..\uart_if_syn_hier_info
....\........\div.bsf
....\........\div_2.bsf
....\........\div_2.v
....\........\filter.bsf
....\........\LED_flush.bsf
....\........\quartus_nativelink_simulation.log
....\........\rcvr.bsf
....\........\simulation
....\........\..........\modelsim
....\........\..........\........\cyclone_atoms.v
....\........\..........\........\modelsim.ini
....\........\..........\........\modelsim_work
....\........\..........\........\.............\@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e
....\........\..........\........\.............\................................\verilog.asm
....\........\..........\........\.............\................................\_primary.dat
....\........\..........\........\.............\................................\_primary.vhd