文件名称:vr_fifo
介绍说明－－下载内容均来自于网络，请自行研究使用
可预取的fifo 的fpga 设计代码，满足异步时钟的操作-Can prefetch the fifo of the FPGA design code, to meet the asynchronous clock operation
(系统自动生成,下载前可以参看下载内容)
下载文件列表
bench
.....\polynome_pkg.vhd
.....\polynome_pkg_body.vhd
.....\vr_fifo_tb.vhd
doc
...\VR_FIFO_spec.doc
par
...\.recordref
...\layer0.sro
...\layer0.tlg
...\rpt_vr_fifo.areasrr
...\rpt_vr_fifo_areasrr.htm
...\stderr.log
...\stdout.log
...\syntmp
...\......\vr_fifo.msg
...\......\vr_fifo.plg
...\......\vr_fifo_flink.htm
...\......\vr_fifo_srr.htm
...\......\vr_fifo_toc.htm
...\traplog.tlg
...\verif
...\.....\vr_fifo.vif
...\vr_fifo.bld
...\vr_fifo.cel
...\vr_fifo.cmd_log
...\vr_fifo.edn
...\vr_fifo.fse
...\vr_fifo.htm
...\vr_fifo.ise
...\vr_fifo.ise_created
...\vr_fifo.ise_ISE_Backup
...\vr_fifo.log
...\vr_fifo.ncd
...\vr_fifo.ncf
...\vr_fifo.ngd
...\vr_fifo.pad
...\vr_fifo.par
...\vr_fifo.pcf
...\vr_fifo.prj
...\vr_fifo.sdc
...\vr_fifo.srd
...\vr_fifo.srm
...\vr_fifo.srr
...\vr_fifo.srs
...\vr_fifo.twr
...\vr_fifo.twx
...\vr_fifo.ucf
...\vr_fifo.unroutes
...\vr_fifo.xpi
...\vr_fifo_compile.tcl
...\vr_fifo_last_par.ncd
...\vr_fifo_map.mrp
...\vr_fifo_map.ncd
...\vr_fifo_map.ngm
...\vr_fifo_map.tcl
...\vr_fifo_pad.csv
...\vr_fifo_pad.txt
...\vr_fifo_summary.html
...\_mh_info
...\_ngo
...\....\netlist.lst
...\....\vr_fifo.ngo
...\_verilog_hintfile
...\_xmsgs
...\......\map.xmsgs
...\......\ngdbuild.xmsgs
...\......\par.xmsgs
...\......\trce.xmsgs
...\......\xst.xmsgs
...\__ISE_repository_vr_fifo.ise_.lock
sim
...\sim.do
...\vsim.wlf
...\wave.do
...\work
...\....\polynome_pkg
...\....\............\body.asm
...\....\............\body.dat
...\....\............\_primary.dat
...\....\............\_vhdl.asm
...\....\vr_fifo
...\....\.......\rtl.asm
...\....\.......\rtl.dat
...\....\.......\_primary.dat
...\....\vr_fifo_tb
...\....\..........\bench.asm
...\....\..........\bench.dat
...\....\..........\_primary.dat
...\....\_info
src
...\vr_fifo_rtl.vhd
.....\polynome_pkg.vhd
.....\polynome_pkg_body.vhd
.....\vr_fifo_tb.vhd
doc
...\VR_FIFO_spec.doc
par
...\.recordref
...\layer0.sro
...\layer0.tlg
...\rpt_vr_fifo.areasrr
...\rpt_vr_fifo_areasrr.htm
...\stderr.log
...\stdout.log
...\syntmp
...\......\vr_fifo.msg
...\......\vr_fifo.plg
...\......\vr_fifo_flink.htm
...\......\vr_fifo_srr.htm
...\......\vr_fifo_toc.htm
...\traplog.tlg
...\verif
...\.....\vr_fifo.vif
...\vr_fifo.bld
...\vr_fifo.cel
...\vr_fifo.cmd_log
...\vr_fifo.edn
...\vr_fifo.fse
...\vr_fifo.htm
...\vr_fifo.ise
...\vr_fifo.ise_created
...\vr_fifo.ise_ISE_Backup
...\vr_fifo.log
...\vr_fifo.ncd
...\vr_fifo.ncf
...\vr_fifo.ngd
...\vr_fifo.pad
...\vr_fifo.par
...\vr_fifo.pcf
...\vr_fifo.prj
...\vr_fifo.sdc
...\vr_fifo.srd
...\vr_fifo.srm
...\vr_fifo.srr
...\vr_fifo.srs
...\vr_fifo.twr
...\vr_fifo.twx
...\vr_fifo.ucf
...\vr_fifo.unroutes
...\vr_fifo.xpi
...\vr_fifo_compile.tcl
...\vr_fifo_last_par.ncd
...\vr_fifo_map.mrp
...\vr_fifo_map.ncd
...\vr_fifo_map.ngm
...\vr_fifo_map.tcl
...\vr_fifo_pad.csv
...\vr_fifo_pad.txt
...\vr_fifo_summary.html
...\_mh_info
...\_ngo
...\....\netlist.lst
...\....\vr_fifo.ngo
...\_verilog_hintfile
...\_xmsgs
...\......\map.xmsgs
...\......\ngdbuild.xmsgs
...\......\par.xmsgs
...\......\trce.xmsgs
...\......\xst.xmsgs
...\__ISE_repository_vr_fifo.ise_.lock
sim
...\sim.do
...\vsim.wlf
...\wave.do
...\work
...\....\polynome_pkg
...\....\............\body.asm
...\....\............\body.dat
...\....\............\_primary.dat
...\....\............\_vhdl.asm
...\....\vr_fifo
...\....\.......\rtl.asm
...\....\.......\rtl.dat
...\....\.......\_primary.dat
...\....\vr_fifo_tb
...\....\..........\bench.asm
...\....\..........\bench.dat
...\....\..........\_primary.dat
...\....\_info
src
...\vr_fifo_rtl.vhd