Nios构成

........\add_constraints_for_ddr_sdram.tcl

........\altpllpll.cmp

........\altpllpll.ppf

........\altpllpll.vhd

........\auto_add_ddr_constraints.tcl

........\auto_verify_ddr_timing.tcl

........\button_pio.vhd

........\clock_0.vhd

........\constraints_out.txt

........\cpu.ocp

........\cpu.vhd

........\cpu_ic_tag_ram.mif

........\cpu_jtag_debug_module.vhd

........\cpu_jtag_debug_module_wrapper.vhd

........\cpu_mult_cell.vhd

........\cpu_ociram_default_contents.mif

........\cpu_rf_ram_a.mif

........\cpu_rf_ram_b.mif

........\cpu_test_bench.vhd

........\ddr_lib_path.tcl

........\ddr_pll_cycloneii.vhd

........\ddr_sdram.cmp

........\ddr_sdram.html

........\ddr_sdram.ppf

........\ddr_sdram.vhd

........\ddr_sdram_auk_ddr_clk_gen.vhd

........\ddr_sdram_auk_ddr_datapath.vhd

........\ddr_sdram_auk_ddr_datapath_pack.vhd

........\ddr_sdram_auk_ddr_dqs_group.vhd

........\ddr_sdram_auk_ddr_sdram.vhd

........\ddr_sdram_ddr_settings.txt

........\ddr_sdram_estimated_data.dat

........\ddr_sdram_example_driver.vhd

........\ddr_sdram_extraction_data.txt

........\ddr_sdram_extraction_log2.txt

........\ddr_sdram_post_summary.txt

........\ddr_sdram_pre_compile_ddr_timing_summary.txt

........\epcs_controller.vhd

........\epcs_controller_boot_rom.hex

........\estimated_data.txt

........\high_res_timer.vhd

........\jtag_uart.vhd

........\lcd_display.vhd

........\led_pio.vhd

........\pll.vhd

........\readme.txt

........\reconfig_request_pio.vhd

........\remove_add_constraints_for_ddr_sdram.tcl

........\seven_seg_pio.vhd

........\standard.asm.rpt.htm

........\standard.bdf

........\standard.done

........\standard.fit.rpt.htm

........\standard.fit.smsg

........\standard.fit.summary

........\standard.flow.rpt.htm

........\standard.jdi

........\standard.map.rpt.htm

........\standard.map.summary

........\standard.pin

........\standard.pof

........\standard.qpf

........\standard.qsf

........\standard.sof

........\standard.tan.rpt.htm

........\standard.tan.summary

........\standard_assignment_defaults.qdf

........\std_2C35.bsf

........\std_2C35.ptf

........\std_2C35.ptf.6.00

........\std_2C35.vhd

........\std_2C35_generation_script

........\std_2C35_setup_quartus.tcl

........\std_2C35_sim

........\............\atail-f.pl

........\............\jtag_uart_input_mutex.dat

........\............\jtag_uart_input_stream.dat

........\............\jtag_uart_output_stream.dat

........\............\uart1_input_data_mutex.dat

........\............\uart1_input_data_stream.dat

........\............\uart1_log_module.txt

........\sysid.vhd

........\sys_clk_timer.vhd

........\testbench

........\.........\ddr_sdram_debug_design_tb.vhd

........\.........\generic_ddr2_sdram.vhd

........\.........\generic_ddr_dimm_model.vhd

........\.........\generic_ddr_sdram.vhd

........\.........\modelsim

........\.........\........\ddr_sdram_ddr_sdram_vsim.tcl

........\.........\........\wave.do

........\uart1.vhd

........\verify_timing_for_ddr_sdram.tcl