VGA接口设计实例及测试程序(源码)

...............................\VGA_example

...............................\...........\vgainterface

...............................\...........\............\cmp_state.ini

...............................\...........\............\code.hex

...............................\...........\............\db

...............................\...........\............\..\altsyncram_fiq.tdf

...............................\...........\............\..\altsyncram_puq.tdf

...............................\...........\............\..\altsyncram_qcr.tdf

...............................\...........\............\..\altsyncram_s1r.tdf

...............................\...........\............\..\cntr_ea7.tdf

...............................\...........\............\..\cntr_vu7.tdf

...............................\...........\............\..\mux_rab.tdf

...............................\...........\............\..\vgainterface.asm.qmsg

...............................\...........\............\..\vgainterface.cmp.cdb

...............................\...........\............\..\vgainterface.cmp.ddb

...............................\...........\............\..\vgainterface.cmp.hdb

...............................\...........\............\..\vgainterface.cmp.rdb

...............................\...........\............\..\vgainterface.cmp.tdb

...............................\...........\............\..\vgainterface.dat_manager.dat

...............................\...........\............\..\vgainterface.db_info

...............................\...........\............\..\vgainterface.fit.qmsg

...............................\...........\............\..\vgainterface.hier_info

...............................\...........\............\..\vgainterface.hif

...............................\...........\............\..\vgainterface.icc

...............................\...........\............\..\vgainterface.map.cdb

...............................\...........\............\..\vgainterface.map.hdb

...............................\...........\............\..\vgainterface.map.qmsg

...............................\...........\............\..\vgainterface.pre_map.hdb

...............................\...........\............\..\vgainterface.project.hdb

...............................\...........\............\..\vgainterface.rtlv.hdb

...............................\...........\............\..\vgainterface.rtlv_sg.cdb

...............................\...........\............\..\vgainterface.rtlv_sg_swap.cdb

...............................\...........\............\..\vgainterface.sgdiff.cdb

...............................\...........\............\..\vgainterface.sgdiff.hdb

...............................\...........\............\..\vgainterface.signalprobe.cdb

...............................\...........\............\..\vgainterface.sim.hdb

...............................\...........\............\..\vgainterface.sim.qmsg

...............................\...........\............\..\vgainterface.sim.rdb

...............................\...........\............\..\vgainterface.sim.vwf

...............................\...........\............\..\vgainterface.sld_design_entry.sci

...............................\...........\............\..\vgainterface.sld_design_entry_dsc.sci

...............................\...........\............\..\vgainterface.syn_hier_info

...............................\...........\............\..\vgainterface.tan.qmsg

...............................\...........\............\..\vgainterface_cmp.qrpt

...............................\...........\............\..\vgainterface_sim.qrpt

...............................\...........\............\serv_req_info.txt

...............................\...........\............\sim.cfg

...............................\...........\............\tsinghua.cmp

...............................\...........\............\tsinghua.mif

...............................\...........\............\tsinghua.vhd

...............................\...........\............\undo_redo.txt

...............................\...........\............\