文件名称:CPU
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verilog 实现的CPU，用Modelsim SE 6.2b 创建的工程，包含测试文件。- CPU of verilog implementation
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下载文件列表
CPU\accum.v
...\addr_decode.v
...\adr.v
...\alu.v
...\clk_gen.v
...\clk_gen.v.bak
...\counter.v
...\CPU.cr.mti
...\CPU.mpf
...\cpu.v
...\cpu.v.bak
...\cputop.v
...\cputop.v.bak
...\datactl.v
...\datactl.v.bak
...\machine.v
...\machinectl.v
...\ram.v
...\register.v
...\register.v.bak
...\rom.v
...\rom.v.bak
...\test1.dat
...\test1.pro
...\test2.dat
...\test2.pro
...\test3.dat
...\test3.pro
...\vsim.wlf
...\work\accum\_primary.dat
...\....\.....\_primary.vhd
...\....\.ddr_decode\_primary.dat
...\....\...........\_primary.vhd
...\....\..r\_primary.dat
...\....\...\_primary.vhd
...\....\.lu\_primary.dat
...\....\...\_primary.vhd
...\....\clk_gen\_primary.dat
...\....\.......\_primary.vhd
...\....\.ounter\_primary.dat
...\....\.......\_primary.vhd
...\....\.pu\_primary.dat
...\....\...\_primary.vhd
...\....\datactl\_primary.dat
...\....\.......\_primary.vhd
...\....\machine\_primary.dat
...\....\.......\_primary.vhd
...\....\.......ctl\_primary.dat
...\....\..........\_primary.vhd
...\....\ram\_primary.dat
...\....\...\_primary.vhd
...\....\.egister\_primary.dat
...\....\........\_primary.vhd
...\....\.om\_primary.dat
...\....\...\_primary.vhd
...\....\t\_primary.dat
...\....\.\_primary.vhd
...\....\_info
...\....\.opt\work_machinectl_fast.asm
...\....\....\work_machinectl_fast.dt2
...\....\....\work__info
...\....\....\_deps
...\....\....1\work_accum_fast.dt2
...\....\.....\work_addr_decode_fast.dt2
...\....\.....\work_adr_fast.asm
...\....\.....\work_adr_fast.dt2
...\....\.....\work_alu_fast.asm
...\....\.....\work_alu_fast.dt2
...\....\.....\work_clk_gen_fast.dt2
...\....\.....\work_counter_fast.dt2
...\....\.....\work_cpu_fast.dt2
...\....\.....\work_datactl_fast.dt2
...\....\.....\work_machinectl_fast.dt2
...\....\.....\work_machine_fast.dt2
...\....\.....\work_ram_fast.dt2
...\....\.....\work_register_fast.dt2
...\....\.....\work_rom_fast.dt2
...\....\.....\work_t_fast.asm
...\....\.....\work_t_fast.dt2
...\....\.....\work__info
...\....\.....\_deps
...\....\accum
...\....\addr_decode
...\....\adr
...\....\alu
...\....\clk_gen
...\....\counter
...\....\cpu
...\....\datactl
...\....\machine
...\....\machinectl
...\....\ram
...\....\register
...\....\rom
...\....\t
...\....\_opt
...\....\_opt1
...\....\_temp
...\work
CPU
...\addr_decode.v
...\adr.v
...\alu.v
...\clk_gen.v
...\clk_gen.v.bak
...\counter.v
...\CPU.cr.mti
...\CPU.mpf
...\cpu.v
...\cpu.v.bak
...\cputop.v
...\cputop.v.bak
...\datactl.v
...\datactl.v.bak
...\machine.v
...\machinectl.v
...\ram.v
...\register.v
...\register.v.bak
...\rom.v
...\rom.v.bak
...\test1.dat
...\test1.pro
...\test2.dat
...\test2.pro
...\test3.dat
...\test3.pro
...\vsim.wlf
...\work\accum\_primary.dat
...\....\.....\_primary.vhd
...\....\.ddr_decode\_primary.dat
...\....\...........\_primary.vhd
...\....\..r\_primary.dat
...\....\...\_primary.vhd
...\....\.lu\_primary.dat
...\....\...\_primary.vhd
...\....\clk_gen\_primary.dat
...\....\.......\_primary.vhd
...\....\.ounter\_primary.dat
...\....\.......\_primary.vhd
...\....\.pu\_primary.dat
...\....\...\_primary.vhd
...\....\datactl\_primary.dat
...\....\.......\_primary.vhd
...\....\machine\_primary.dat
...\....\.......\_primary.vhd
...\....\.......ctl\_primary.dat
...\....\..........\_primary.vhd
...\....\ram\_primary.dat
...\....\...\_primary.vhd
...\....\.egister\_primary.dat
...\....\........\_primary.vhd
...\....\.om\_primary.dat
...\....\...\_primary.vhd
...\....\t\_primary.dat
...\....\.\_primary.vhd
...\....\_info
...\....\.opt\work_machinectl_fast.asm
...\....\....\work_machinectl_fast.dt2
...\....\....\work__info
...\....\....\_deps
...\....\....1\work_accum_fast.dt2
...\....\.....\work_addr_decode_fast.dt2
...\....\.....\work_adr_fast.asm
...\....\.....\work_adr_fast.dt2
...\....\.....\work_alu_fast.asm
...\....\.....\work_alu_fast.dt2
...\....\.....\work_clk_gen_fast.dt2
...\....\.....\work_counter_fast.dt2
...\....\.....\work_cpu_fast.dt2
...\....\.....\work_datactl_fast.dt2
...\....\.....\work_machinectl_fast.dt2
...\....\.....\work_machine_fast.dt2
...\....\.....\work_ram_fast.dt2
...\....\.....\work_register_fast.dt2
...\....\.....\work_rom_fast.dt2
...\....\.....\work_t_fast.asm
...\....\.....\work_t_fast.dt2
...\....\.....\work__info
...\....\.....\_deps
...\....\accum
...\....\addr_decode
...\....\adr
...\....\alu
...\....\clk_gen
...\....\counter
...\....\cpu
...\....\datactl
...\....\machine
...\....\machinectl
...\....\ram
...\....\register
...\....\rom
...\....\t
...\....\_opt
...\....\_opt1
...\....\_temp
...\work
CPU