文件名称:reload_fir

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [PDF]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 15.95mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • 林**
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  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

这是我在Xilinx公司的FPGA上实现的FIR滤波器,调用的内部核,其特色是可以用较少的资源实现该功能,而且可以实现参数重载,即从外部MCU设置FIR滤波器的参数-This is my Xilinx FPGA to achieve the FIR filter, called internal audit, its characteristics can be achieved with fewer resources to this function, and the overload parameters can be achieved, that is, from an external MCU to set the parameters of FIR Filter
(系统自动生成,下载前可以参看下载内容)

下载文件列表

core_resources.txt

dds.asy

dds.ngc

dds.sym

dds.v

dds.veo

dds.vhd

dds.vho

dds.xco

dds_cs.cdc

dds_flist.txt

dds_icon.asy

dds_icon.ncf

dds_icon.v

dds_icon.veo

dds_icon.vhd

dds_icon.vho

dds_icon.xco

dds_icon_flist.txt

dds_icon_readme.txt

dds_icon_xmdf.tcl

dds_readme.txt

dds_SINCOS_TABLE_TRIG_ROM.mif

dds_tbw.ant

dds_tbw.fdo

dds_tbw.jhd

dds_tbw.tbw

dds_tbw.tfw

dds_tbw.udo

dds_tbw.xwv

dds_tbw.xwv_bak

dds_tbw_beh.prj

dds_tbw_bencher.prj

dds_tbw_isim_beh.exe

dds_tbw_isim_beh.wfs

dds_tbw_wave.fdo

dds_vio.asy

dds_vio.cdc

dds_vio.ncf

dds_vio.v

dds_vio.veo

dds_vio.vhd

dds_vio.vho

dds_vio.xco

dds_vio_flist.txt

dds_vio_readme.txt

dds_vio_xmdf.tcl

dds_xmdf.tcl

dist_mem_gen_ds322.pdf

dist_mem_gen_readme.txt

every_frediv.v

filter.v

fir.asy

fir.mif

fir.ngc

fir.sym

fir.v

fir.veo

fir.vhd

fir.vho

fir.xco

firCOEFF_auto0.mif

firCOEFF_auto1.mif

firCOEFF_auto2.mif

firfilt_decode_rom.mif

fir_coe

.......\hp_coe.coe

.......\lp_coe.coe

fir_fir_compiler_v3_2_xst_1.lso

fir_fir_compiler_v3_2_xst_1.ngc_xst.xrpt

fir_fir_compiler_v3_2_xst_1_vhdl.prj

fir_fir_compiler_v3_2_xst_1_xsd

...............................\blk_mem_gen_v2_5

...............................\................\sub00

...............................\................\vlg77

...............................\................\.....\ramb36sdp__wrap.bin

...............................\c_mux_bit_v9_0

...............................\..............\hdllib.ref

...............................\..............\hdpdeps.ref

...............................\..............\sub00

...............................\..............\.....\vhpl00.vho

...............................\..............\.....\vhpl01.vho

...............................\..............\.....\vhpl02.vho

...............................\..............\.....\vhpl03.vho

...............................\..............\.....\vhpl04.vho

...............................\..............\.....\vhpl05.vho

...............................\..............\.....\vhpl06.vho

...............................\..............\.....\vhpl07.vho

...............................\..............\.....\vhpl08.vho

...............................\..............\.....\vhpl09.vho

...............................\..............\.....\vhpl10.vho

...............................\..............\.....\vhpl11.vho

...............................\..............\.....\vhpl12.vho

...............................\..............\.....\vhpl13.vho

...............................\..............\.....\vhpl14.vho

...............................\c_reg_fd_v9_0

...............................\.............\hdllib.ref

...............................\.............\hdpdeps.ref

...............................\.............\sub00

...............................\.............\.....\vhpl00.vho

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