16-bit_cpu_design - 源码下载|嵌入式/单片机编程|微处理器(ARM/PowerPC等)|源代码

详细介绍了如何设计一个简单的16位cpu.其中包含了从最基础的指令系统开始到最复杂的cu控制器的设计思路，方案.最后还介绍了一些有关vhdl语言的用法,并给出了具体的cpu部件的vhdl代码,从而帮助大家更为深刻的学习如何设计一个简单的cpu-Described in detail how to design a simple 16-bit cpu. Which contains the most basic instruction from the beginning to the most complex cu controller design ideas, program. Finally the author describes some of the vhdl language usage, and gives vhdl cpu specific parts of the code to help you more deeply to learn how to design a simple cpu

下载文件列表

16位实验CPU设计实例介绍.doc

MyCPU\cmp_state.ini

.....\db\MyCPU.asm.qmsg

.....\..\MyCPU.cbx.xml

.....\..\MyCPU.cmp.cdb

.....\..\MyCPU.cmp.hdb

.....\..\MyCPU.cmp.rdb

.....\..\MyCPU.cmp.tdb

.....\..\MyCPU.cmp0.ddb

.....\..\MyCPU.db_info

.....\..\MyCPU.eco.cdb

.....\..\MyCPU.eda.qmsg

.....\..\MyCPU.fit.qmsg

.....\..\MyCPU.frm.hdb

.....\..\MyCPU.hier_info

.....\..\MyCPU.hif

.....\..\MyCPU.map.cdb

.....\..\MyCPU.map.hdb

.....\..\MyCPU.map.qmsg

.....\..\MyCPU.pre_map.cdb

.....\..\MyCPU.pre_map.hdb

.....\..\MyCPU.psp

.....\..\MyCPU.rpp.qmsg

.....\..\MyCPU.rtlv.hdb

.....\..\MyCPU.rtlv_sg.cdb

.....\..\MyCPU.rtlv_sg_swap.cdb

.....\..\MyCPU.sgate.rvd

.....\..\MyCPU.sgdiff.cdb

.....\..\MyCPU.sgdiff.hdb

.....\..\MyCPU.signalprobe.cdb

.....\..\MyCPU.sld_design_entry.sci

.....\..\MyCPU.sld_design_entry_dsc.sci

.....\..\MyCPU.swb.qmsg

.....\..\MyCPU.syn_hier_info

.....\..\MyCPU.tan.qmsg

.....\..\MyCPU_cmp.qrpt

.....\decoder_2_to_4.vhd

.....\decoder_unit.vhd

.....\exe_unit.vhd

.....\exp_cpu_components.vhd

.....\instru_fetch.vhd

.....\memory_unit.vhd

.....\mux_4_to_1.vhd

.....\MyCPU.asm.rpt

.....\MyCPU.cdf

.....\MyCPU.done

.....\MyCPU.eda.rpt

.....\MyCPU.fit.eqn

.....\MyCPU.fit.rpt

.....\MyCPU.fit.summary

.....\MyCPU.flow.rpt

.....\MyCPU.map.eqn

.....\MyCPU.map.rpt

.....\MyCPU.map.summary

.....\MyCPU.pin

.....\MyCPU.pof

.....\MyCPU.qpf

.....\MyCPU.qsf

.....\MyCPU.qws

.....\MyCPU.sof

.....\MyCPU.tan.rpt

.....\MyCPU.tan.summary

.....\MyCPU.vhd

.....\MyCPU.vwf

.....\reg.vhd

.....\regfile.vhd

.....\simulation\modelsim\MyCPU.vho

.....\..........\........\MyCPU_modelsim.xrf

.....\..........\........\MyCPU_vhd.sdo

.....\test1.txt

.....\.iming\primetime\MyCPU.vho

.....\......\.........\MyCPU_pt_vhd.tcl

.....\......\.........\MyCPU_vhd.sdo

.....\zha.txt

.....\simulation\modelsim

.....\timing\primetime

.....\db

.....\simulation

.....\timing

MyCPU

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