FPGAcodeXYZ\FPGA code\async_receiver.v

...........\.........\db\DE2_TOP.cbx.xml

...........\.........\..\DE2_TOP.cmp.rdb

...........\.........\..\DE2_TOP.cmp_merge.kpt

...........\.........\..\DE2_TOP.db_info

...........\.........\..\DE2_TOP.eco.cdb

...........\.........\..\DE2_TOP.hier_info

...........\.........\..\DE2_TOP.hif

...........\.........\..\DE2_TOP.lpc.html

...........\.........\..\DE2_TOP.lpc.rdb

...........\.........\..\DE2_TOP.lpc.txt

...........\.........\..\DE2_TOP.map.bpm

...........\.........\..\DE2_TOP.map.cdb

...........\.........\..\DE2_TOP.map.ecobp

...........\.........\..\DE2_TOP.map.hdb

...........\.........\..\DE2_TOP.map.kpt

...........\.........\..\DE2_TOP.map.logdb

...........\.........\..\DE2_TOP.map.qmsg

...........\.........\..\DE2_TOP.map_bb.cdb

...........\.........\..\DE2_TOP.map_bb.hdb

...........\.........\..\DE2_TOP.map_bb.logdb

...........\.........\..\DE2_TOP.pre_map.cdb

...........\.........\..\DE2_TOP.pre_map.hdb

...........\.........\..\DE2_TOP.rtlv.hdb

...........\.........\..\DE2_TOP.rtlv_sg.cdb

...........\.........\..\DE2_TOP.rtlv_sg_swap.cdb

...........\.........\..\DE2_TOP.sgdiff.cdb

...........\.........\..\DE2_TOP.sgdiff.hdb

...........\.........\..\DE2_TOP.sld_design_entry.sci

...........\.........\..\DE2_TOP.sld_design_entry_dsc.sci

...........\.........\..\DE2_TOP.smart_action.txt

...........\.........\..\DE2_TOP.smp_dump.txt

...........\.........\..\DE2_TOP.syn_hier_info

...........\.........\..\DE2_TOP.tis_db_list.ddb

...........\.........\..\DE2_TOP.tmw_info

...........\.........\..\logic_util_heursitic.dat

...........\.........\DE2_TOP.done

...........\.........\DE2_TOP.flow.rpt

...........\.........\DE2_TOP.map.rpt

...........\.........\DE2_TOP.map.smsg

...........\.........\DE2_TOP.map.summary

...........\.........\DE2_TOP.qpf

...........\.........\DE2_TOP.qsf

...........\.........\DE2_TOP.qws

...........\.........\DE2_TOP.v

...........\.........\incremental_db\compiled_partitions\DE2_TOP.root_partition.map.cdb

...........\.........\..............\...................\DE2_TOP.root_partition.map.dpi

...........\.........\..............\...................\DE2_TOP.root_partition.map.hdb

...........\.........\..............\...................\DE2_TOP.root_partition.map.kpt

...........\.........\..............\...................\DE2_TOP.root_partition.merge_hb.atm

...........\.........\..............\README

...........\.........\reloj_fast.v

...........\.........\Reset_Delay.v

...........\.........\RS232_Controller.v

...........\.........\SEG7_LUT.v

...........\.........\VGA_Ctrl.v

...........\.........\VGA_PLL.v

...........\.........\incremental_db\compiled_partitions

...........\.........\db

...........\.........\incremental_db

...........\FPGA code

FPGAcodeXYZ