文件名称:aes_core
介绍说明－－下载内容均来自于网络，请自行研究使用
aes 加密模块，通过这个例子可以学习专业集成电路设计中数字电路设计的一些方法，带你入门设计-aes encryption module can learn through the example of professional digital circuit design integrated circuit design in some way, take you on design
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下载文件列表
aes_core\.svn\all-wcprops
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........\....\format
........\branches\.svn\all-wcprops
........\........\....\dir-prop-base
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........\tags\.svn\all-wcprops
........\....\....\dir-prop-base
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........\....\....\format
........\....\start\.svn\all-wcprops
........\....\.....\....\entries
........\....\.....\....\format
........\....\.....\....\text-base\vim_session.vim.svn-base
........\....\.....\bench\.svn\all-wcprops
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........\....\.....\.....\....\format
........\....\.....\.....\verilog\.svn\all-wcprops
........\....\.....\.....\.......\....\entries
........\....\.....\.....\.......\....\format
........\....\.....\.....\.......\....\text-base\test_bench_top.v.svn-base
........\....\.....\.....\.......\test_bench_top.v
........\....\.....\doc\.svn\all-wcprops
........\....\.....\...\....\entries
........\....\.....\...\....\format
........\....\.....\...\....\prop-base\aes.pdf.svn-base
........\....\.....\...\....\text-base\aes.pdf.svn-base
........\....\.....\...\aes.pdf
........\....\.....\rtl\.svn\all-wcprops
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........\....\.....\...\....\format
........\....\.....\...\verilog\.svn\all-wcprops
........\....\.....\...\.......\....\entries
........\....\.....\...\.......\....\format
........\....\.....\...\.......\....\text-base\aes_cipher_top.v.svn-base
........\....\.....\...\.......\....\.........\aes_inv_cipher_top.v.svn-base
........\....\.....\...\.......\....\.........\aes_inv_sbox.v.svn-base
........\....\.....\...\.......\....\.........\aes_key_expand_128.v.svn-base
........\....\.....\...\.......\....\.........\aes_rcon.v.svn-base
........\....\.....\...\.......\....\.........\aes_sbox.v.svn-base
........\....\.....\...\.......\aes_cipher_top.v
........\....\.....\...\.......\aes_inv_cipher_top.v
........\....\.....\...\.......\aes_inv_sbox.v
........\....\.....\...\.......\aes_key_expand_128.v
........\....\.....\...\.......\aes_rcon.v
........\....\.....\...\.......\aes_sbox.v
........\....\.....\sim\.svn\all-wcprops
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........\....\.....\...\....\format
........\....\.....\...\rtl_sim\.svn\all-wcprops
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........\....\.....\...\.......\....\format
........\....\.....\...\.......\bin\.svn\all-wcprops
........\....\.....\...\.......\...\....\entries
........\....\.....\...\.......\...\....\format
........\....\.....\...\.......\...\....\prop-base\Makefile.svn-base
........\....\.....\...\.......\...\....\text-base\Makefile.svn-base
........\....\.....\...\.......\...\Makefile
........\....\.....\...\.......\run\.svn\all-wcprops
........\....\.....\...\.......\...\....\entries
........\....\.....\...\.......\...\....\format
........\....\.....\...\.......\...\waves\.svn\all-wcprops
........\....\.....\...\.......\...\.....\....\entries
........\....\.....\...\.......\...\.....\....\format
........\....\.....\...\.......\...\.....\....\text-base\waves.do.svn-base
........\....\.....\...\.......\...\.....\waves.do
........\....\.....\.yn\.svn\all-wcprops
........\....\.....\...\....\entries
........\....\.....\...\....\format
........\....\.....\...\bin\.svn\all-wcprops
........\....\.....\...\...\....\entries
........\....\.....\...\...\....\format
........\....\.....\...\...\....\text-base\comp.dc.svn-base
........\....\.....\...\...\....\.........\design_spec.dc.svn-base
........\....\.....\...\...\....\.........\lib_spec.dc.svn-base
........\....\.....\...\...\....\.........\read.dc.svn-base
........\....\.....\...\...\comp.dc
........\....\.....\...\...\design_spec.dc
........\....\.....\...\...\lib_spec.dc
........\....\.....\...\...\read.dc
........\....\.....\vim_session.vim
........\.runk\.svn\all-wcprops
........\.....\....\dir-prop-base
........\.....\....\entries
........\.....\....\format
........\.....\....\text-base\vim_session.vim.svn-base
........\.....\bench\.svn\all-wcprops
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...
........\....\entries
........\....\format
........\branches\.svn\all-wcprops
........\........\....\dir-prop-base
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........\........\....\format
........\tags\.svn\all-wcprops
........\....\....\dir-prop-base
........\....\....\entries
........\....\....\format
........\....\start\.svn\all-wcprops
........\....\.....\....\entries
........\....\.....\....\format
........\....\.....\....\text-base\vim_session.vim.svn-base
........\....\.....\bench\.svn\all-wcprops
........\....\.....\.....\....\entries
........\....\.....\.....\....\format
........\....\.....\.....\verilog\.svn\all-wcprops
........\....\.....\.....\.......\....\entries
........\....\.....\.....\.......\....\format
........\....\.....\.....\.......\....\text-base\test_bench_top.v.svn-base
........\....\.....\.....\.......\test_bench_top.v
........\....\.....\doc\.svn\all-wcprops
........\....\.....\...\....\entries
........\....\.....\...\....\format
........\....\.....\...\....\prop-base\aes.pdf.svn-base
........\....\.....\...\....\text-base\aes.pdf.svn-base
........\....\.....\...\aes.pdf
........\....\.....\rtl\.svn\all-wcprops
........\....\.....\...\....\entries
........\....\.....\...\....\format
........\....\.....\...\verilog\.svn\all-wcprops
........\....\.....\...\.......\....\entries
........\....\.....\...\.......\....\format
........\....\.....\...\.......\....\text-base\aes_cipher_top.v.svn-base
........\....\.....\...\.......\....\.........\aes_inv_cipher_top.v.svn-base
........\....\.....\...\.......\....\.........\aes_inv_sbox.v.svn-base
........\....\.....\...\.......\....\.........\aes_key_expand_128.v.svn-base
........\....\.....\...\.......\....\.........\aes_rcon.v.svn-base
........\....\.....\...\.......\....\.........\aes_sbox.v.svn-base
........\....\.....\...\.......\aes_cipher_top.v
........\....\.....\...\.......\aes_inv_cipher_top.v
........\....\.....\...\.......\aes_inv_sbox.v
........\....\.....\...\.......\aes_key_expand_128.v
........\....\.....\...\.......\aes_rcon.v
........\....\.....\...\.......\aes_sbox.v
........\....\.....\sim\.svn\all-wcprops
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........\....\.....\...\....\format
........\....\.....\...\rtl_sim\.svn\all-wcprops
........\....\.....\...\.......\....\entries
........\....\.....\...\.......\....\format
........\....\.....\...\.......\bin\.svn\all-wcprops
........\....\.....\...\.......\...\....\entries
........\....\.....\...\.......\...\....\format
........\....\.....\...\.......\...\....\prop-base\Makefile.svn-base
........\....\.....\...\.......\...\....\text-base\Makefile.svn-base
........\....\.....\...\.......\...\Makefile
........\....\.....\...\.......\run\.svn\all-wcprops
........\....\.....\...\.......\...\....\entries
........\....\.....\...\.......\...\....\format
........\....\.....\...\.......\...\waves\.svn\all-wcprops
........\....\.....\...\.......\...\.....\....\entries
........\....\.....\...\.......\...\.....\....\format
........\....\.....\...\.......\...\.....\....\text-base\waves.do.svn-base
........\....\.....\...\.......\...\.....\waves.do
........\....\.....\.yn\.svn\all-wcprops
........\....\.....\...\....\entries
........\....\.....\...\....\format
........\....\.....\...\bin\.svn\all-wcprops
........\....\.....\...\...\....\entries
........\....\.....\...\...\....\format
........\....\.....\...\...\....\text-base\comp.dc.svn-base
........\....\.....\...\...\....\.........\design_spec.dc.svn-base
........\....\.....\...\...\....\.........\lib_spec.dc.svn-base
........\....\.....\...\...\....\.........\read.dc.svn-base
........\....\.....\...\...\comp.dc
........\....\.....\...\...\design_spec.dc
........\....\.....\...\...\lib_spec.dc
........\....\.....\...\...\read.dc
........\....\.....\vim_session.vim
........\.runk\.svn\all-wcprops
........\.....\....\dir-prop-base
........\.....\....\entries
........\.....\....\format
........\.....\....\text-base\vim_session.vim.svn-base
........\.....\bench\.svn\all-wcprops
........\.....\.....\....\entries
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