文件名称:uart_wb
介绍说明－－下载内容均来自于网络，请自行研究使用
兼容wishbone bus的uart模块，方便用户修改，时候初学者学习-Compatible with wishbone bus the uart module, user-friendly changes beginners to learn when
(系统自动生成,下载前可以参看下载内容)
下载文件列表
uart_wb\eval_params.v
.......\rtl\intface.v
.......\...\modem.v
.......\...\pmi_fifo.v
.......\...\rxcver.v
.......\...\rxcver_fifo.v
.......\...\txcver_fifo.v
.......\...\txcver_fifo.v.bak
.......\...\txmitt.v
.......\...\uart_core.v
.......\uart_core.xml
.......\uart_core_tb.v
.......\uart_core_tb.v.bak
.......\uart_wb_tb.cr.mti
.......\uart_wb_tb.mpf
.......\vsim.wlf
.......\work\intface\verilog.asm
.......\....\.......\verilog.rw
.......\....\.......\_primary.dat
.......\....\.......\_primary.dbs
.......\....\.......\_primary.vhd
.......\....\modem\verilog.asm
.......\....\.....\verilog.rw
.......\....\.....\_primary.dat
.......\....\.....\_primary.dbs
.......\....\.....\_primary.vhd
.......\....\pmi_fifo\_primary.dat
.......\....\........\_primary.dbs
.......\....\........\_primary.vhd
.......\....\rxcver\verilog.asm
.......\....\......\verilog.rw
.......\....\......\_primary.dat
.......\....\......\_primary.dbs
.......\....\......\_primary.vhd
.......\....\......_fifo\_primary.dat
.......\....\...........\_primary.dbs
.......\....\...........\_primary.vhd
.......\....\txcver_fifo\_primary.dat
.......\....\...........\_primary.dbs
.......\....\...........\_primary.vhd
.......\....\..mitt\verilog.asm
.......\....\......\verilog.rw
.......\....\......\_primary.dat
.......\....\......\_primary.dbs
.......\....\......\_primary.vhd
.......\....\uart_core\verilog.asm
.......\....\.........\verilog.rw
.......\....\.........\_primary.dat
.......\....\.........\_primary.dbs
.......\....\.........\_primary.vhd
.......\....\........._tb\verilog.asm
.......\....\............\verilog.rw
.......\....\............\_primary.dat
.......\....\............\_primary.dbs
.......\....\............\_primary.vhd
.......\....\_info
.......\....\.temp\vlog1y9r4r
.......\....\.....\vloga2g8vi
.......\....\.....\vloggg8rg4
.......\....\.....\vlogii3bnt
.......\....\.....\vlogkwd9bf
.......\....\.....\vlogq7btzf
.......\....\.....\vlogqbhfnr
.......\....\.....\vlogsw5614
.......\....\_vmake
.......\....\intface
.......\....\modem
.......\....\pmi_fifo
.......\....\rxcver
.......\....\rxcver_fifo
.......\....\txcver_fifo
.......\....\txmitt
.......\....\uart_core
.......\....\uart_core_tb
.......\....\_temp
.......\rtl
.......\work
uart_wb
.......\rtl\intface.v
.......\...\modem.v
.......\...\pmi_fifo.v
.......\...\rxcver.v
.......\...\rxcver_fifo.v
.......\...\txcver_fifo.v
.......\...\txcver_fifo.v.bak
.......\...\txmitt.v
.......\...\uart_core.v
.......\uart_core.xml
.......\uart_core_tb.v
.......\uart_core_tb.v.bak
.......\uart_wb_tb.cr.mti
.......\uart_wb_tb.mpf
.......\vsim.wlf
.......\work\intface\verilog.asm
.......\....\.......\verilog.rw
.......\....\.......\_primary.dat
.......\....\.......\_primary.dbs
.......\....\.......\_primary.vhd
.......\....\modem\verilog.asm
.......\....\.....\verilog.rw
.......\....\.....\_primary.dat
.......\....\.....\_primary.dbs
.......\....\.....\_primary.vhd
.......\....\pmi_fifo\_primary.dat
.......\....\........\_primary.dbs
.......\....\........\_primary.vhd
.......\....\rxcver\verilog.asm
.......\....\......\verilog.rw
.......\....\......\_primary.dat
.......\....\......\_primary.dbs
.......\....\......\_primary.vhd
.......\....\......_fifo\_primary.dat
.......\....\...........\_primary.dbs
.......\....\...........\_primary.vhd
.......\....\txcver_fifo\_primary.dat
.......\....\...........\_primary.dbs
.......\....\...........\_primary.vhd
.......\....\..mitt\verilog.asm
.......\....\......\verilog.rw
.......\....\......\_primary.dat
.......\....\......\_primary.dbs
.......\....\......\_primary.vhd
.......\....\uart_core\verilog.asm
.......\....\.........\verilog.rw
.......\....\.........\_primary.dat
.......\....\.........\_primary.dbs
.......\....\.........\_primary.vhd
.......\....\........._tb\verilog.asm
.......\....\............\verilog.rw
.......\....\............\_primary.dat
.......\....\............\_primary.dbs
.......\....\............\_primary.vhd
.......\....\_info
.......\....\.temp\vlog1y9r4r
.......\....\.....\vloga2g8vi
.......\....\.....\vloggg8rg4
.......\....\.....\vlogii3bnt
.......\....\.....\vlogkwd9bf
.......\....\.....\vlogq7btzf
.......\....\.....\vlogqbhfnr
.......\....\.....\vlogsw5614
.......\....\_vmake
.......\....\intface
.......\....\modem
.......\....\pmi_fifo
.......\....\rxcver
.......\....\rxcver_fifo
.......\....\txcver_fifo
.......\....\txmitt
.......\....\uart_core
.......\....\uart_core_tb
.......\....\_temp
.......\rtl
.......\work
uart_wb