文件名称:Asynchronous-FIFO-Design
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异步FIFO设计,一共包含6个模块,使用的硬件描述语言verilog。-Asynchronous FIFO design,including six modules.HDL language is verilog.
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Asynchronous FIFO Design
........................\fifo.v
........................\fifomem.v
........................\rptr_empty.v
........................\sync_r2w.v
........................\sync_w2r.v
........................\wptr_full.v
........................\fifo.v
........................\fifomem.v
........................\rptr_empty.v
........................\sync_r2w.v
........................\sync_w2r.v
........................\wptr_full.v