文件名称:VERILOG

  • 所属分类:
  • 书籍源码
  • 资源属性:
  • [VHDL] [源码]
  • 上传时间:
  • 2012-12-17
  • 文件大小:
  • 168kb
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  • 0次
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  • l**
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王金明老师的数字系统设计与Verilog HDL中,讲述的100个实例的Verilog源代码-Wang Jinming teacher " Digital System Design with Verilog HDL" about 100 instances of Verilog source code
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王金明老师讲述的100个Verilog\Verilog设计示例(王金明)\chap10\acc.v

............................\.......................\......\accn.v

............................\.......................\......\add8.v

............................\.......................\......\adder8.v

............................\.......................\......\block1.v

............................\.......................\......\block2.v

............................\.......................\......\block3.v

............................\.......................\......\block4.v

............................\.......................\......\control.v

............................\.......................\......\fsm.v

............................\.......................\......\longframe1.v

............................\.......................\......\longframe2.v

............................\.......................\......\pipeline.v

............................\.......................\......\reg8.v

............................\.......................\......\resource1.v

............................\.......................\......\resource2.v

............................\.......................\.....1\account.v

............................\.......................\......\add_ahead.v

............................\.......................\......\add_bx.v

............................\.......................\......\add_jl.v

............................\.......................\......\add_tree.v

............................\.......................\......\clock.v

............................\.......................\......\control.v

............................\.......................\......\count10.v

............................\.......................\......\fre_ctrl.v

............................\.......................\......\fsm.v

............................\.......................\......\latch_16.v

............................\.......................\......\mult.v

............................\.......................\......\paobiao.v

............................\.......................\......\sell.v

............................\.......................\......\song.v

............................\.......................\......\traffic.v

............................\.......................\.....2\correlator.v

............................\.......................\......\crc.v

............................\.......................\......\cycle.v

............................\.......................\......\decoder1.v

............................\.......................\......\decoder2.v

............................\.......................\......\fir.v

............................\.......................\......\linear.v

............................\.......................\......\mult4x4.v

............................\.......................\....3\adder4.v

............................\.......................\.....\adder_tp.v

............................\.......................\.....\aoi.v

............................\.......................\.....\count4.v

............................\.......................\.....\count4_tp.v

............................\.......................\....5\adder.v

............................\.......................\.....\adder16.v

............................\.......................\.....\alu.v

............................\.......................\.....\block.v

............................\.......................\.....\buried_ff.v

............................\.......................\.....\compile.v

............................\.......................\.....\count.v

............................\.......................\.....\count60.v

............................\.......................\.....\decode4_7.v

............................\.......................\.....\loop1.v

............................\.......................\.....\loop2.v

............................\.......................\.....\loop3.v

............................\.......................\.....\mult_for.v

............................\.......................\.....\mult_repeat.v

....................

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