文件名称:phase_test
介绍说明－－下载内容均来自于网络，请自行研究使用
VHDL,简易音频数字相位表的设计与实现 数字相位测量仪在工业领域中经常用到的一般测量工具，主要应用与同频率正弦信号间的相位差的测量显示。
本系统采用FPGA实现测量的核心部分，主要由数字鉴相、累加计数器、控制器以及寄存与显示译码电路组成。该系统硬件电路简单，整个系统采用硬件描述语言VHDL作为系统内部硬件结构的描述手段，在XILINX公司的ISE9.1的软件支持下完成。可以对20Hz~20kHz频率范围内的音频信号进行采样鉴相处理，并将数据传回FPGA进行相位差计数累加、测量运算，最后送显示译码电路显示，测相范围为 ，相位测量误差 < 。
经测试结果验证，本系统充分利用FPGA对数据的高速处理能力，是系统设计高效、可靠，处理速度快，稳定性高，易于实现。
-VHDL, simple audio digital phase Table Design and Implementation of the digital phase meter general measurement tools are often used in the industrial field, the measurement of the phase difference between the main application with the same frequency sinusoidal signal. The system uses the FPGA implementation of the core part of the measurement, mainly by the digital phase, cumulative counter, the decoding circuit of the controller as well as storage and display. The system hardware circuit is simple, and the entire system using hardware descr iption language VHDL system means a descr iption of the internal hardware structure, completed in the XILINX company ISE9.1 software support. The audio signal in the frequency range of 20Hz ~ 20kHz sampling KAM-phase process, and the data returned FPGA retardation counted accumulation measuring operation, and finally sent to the decoding circuit, the scope of the measurement phase, the phase measurement error < . The test results verify the full u
本系统采用FPGA实现测量的核心部分，主要由数字鉴相、累加计数器、控制器以及寄存与显示译码电路组成。该系统硬件电路简单，整个系统采用硬件描述语言VHDL作为系统内部硬件结构的描述手段，在XILINX公司的ISE9.1的软件支持下完成。可以对20Hz~20kHz频率范围内的音频信号进行采样鉴相处理，并将数据传回FPGA进行相位差计数累加、测量运算，最后送显示译码电路显示，测相范围为 ，相位测量误差 < 。
经测试结果验证，本系统充分利用FPGA对数据的高速处理能力，是系统设计高效、可靠，处理速度快，稳定性高，易于实现。
-VHDL, simple audio digital phase Table Design and Implementation of the digital phase meter general measurement tools are often used in the industrial field, the measurement of the phase difference between the main application with the same frequency sinusoidal signal. The system uses the FPGA implementation of the core part of the measurement, mainly by the digital phase, cumulative counter, the decoding circuit of the controller as well as storage and display. The system hardware circuit is simple, and the entire system using hardware descr iption language VHDL system means a descr iption of the internal hardware structure, completed in the XILINX company ISE9.1 software support. The audio signal in the frequency range of 20Hz ~ 20kHz sampling KAM-phase process, and the data returned FPGA retardation counted accumulation measuring operation, and finally sent to the decoding circuit, the scope of the measurement phase, the phase measurement error < . The test results verify the full u
(系统自动生成,下载前可以参看下载内容)
下载文件列表
phase_test\top.xpi
..........\top_pad.csv
..........\BCD_CODE.prj
..........\BCD_CODE.stx
..........\BCD_CODE.vhd
..........\BCD_CODE.xst
..........\phase_test.xise
..........\control.vhd
..........\controller.prj
..........\controller.stx
..........\controller.vhd
..........\controller.xst
..........\controller_vhdl.prj
..........\Counter_4096.prj
..........\Counter_4096.stx
..........\Counter_4096.vhd
..........\Counter_4096.xst
..........\Counter_4096_vhdl.prj
..........\device_usage_statistics.html
..........\display.prj
..........\display.stx
..........\display.vhd
..........\display.xst
..........\top.pad
..........\top_pad.txt
..........\top.ncd
..........\jianxiang.prj
..........\jianxiang.stx
..........\jianxiang.vhd
..........\jianxiang.xst
..........\jianxiang_vhdl.prj
..........\ll.ise_ISE_Backup
..........\ll.ntrc_log
..........\M_k_counter.prj
..........\M_k_counter.stx
..........\M_k_counter.vhd
..........\M_k_counter.xst
..........\top.unroutes
..........\BCD_CODE.spl
..........\pepExtractor.prj
..........\M_k_counter.spl
..........\phase_test.ise_ISE_Backup
..........\phase_test.ntrc_log
..........\top.bgn
..........\top.bit
..........\BCD_CODE.sym
..........\top.cmd_log
..........\top.drc
..........\top.lso
..........\__ISE_repository_phase_test.ise_.lock
..........\jianxiang.spl
..........\top.pcf
..........\top.prj
..........\top.spl
..........\top.stx
..........\top.sym
..........\top.syr
..........\top.twr
..........\top.twx
..........\top.ucf
..........\jianxiang.sym
..........\top.ut
..........\top.vhd
..........\display.spl
..........\top.xst
..........\top_fpe.prj
..........\top_guide.ncd
..........\M_k_counter.sym
..........\Counter_4096.spl
..........\top_prev_built.ngd
..........\top_summary.html
..........\Counter_4096.sym
..........\controller.spl
..........\__ISE_repository_ll.ise_.lock
..........\controller.sym
..........\display.sym
..........\_xmsgs\bitgen.xmsgs
..........\......\fuse.xmsgs
..........\......\vhpcomp.xmsgs
..........\......\pn_parser.xmsgs
..........\......\xst.xmsgs
..........\......\ngdbuild.xmsgs
..........\......\map.xmsgs
..........\......\par.xmsgs
..........\......\trce.xmsgs
..........\.ngo\netlist.lst
..........\top.vf
..........\top.sch
..........\top.jhd
..........\MK.vhd
..........\top_vhdl.prj
..........\top.ngr
..........\top.bld
..........\top.ngc
..........\top.ngd
..........\top_map.mrp
..........\top_map.map
..........\top_map.ngm
..........\top_map.ncd
..........\top_usage.xml