文件名称:can
介绍说明－－下载内容均来自于网络，请自行研究使用
一个典型的CAN总线的VHDL程序，非常有参考价值-A typical CAN bus VHDL program, a very valuable reference! !
(系统自动生成,下载前可以参看下载内容)
下载文件列表
can\bench\CVS\Entries
...\.....\...\Repository
...\.....\...\Root
...\.....\CVS
...\.....\verilog\can_testbench.v
...\.....\.......\can_testbench_defines.v
...\.....\.......\CVS\Entries
...\.....\.......\...\Repository
...\.....\.......\...\Root
...\.....\.......\CVS
...\.....\.......\timescale.v
...\.....\verilog
...\bench
...\CVS\Entries
...\...\Repository
...\...\Root
...\CVS
...\doc\CVS\Entries
...\...\...\Repository
...\...\...\Root
...\...\CVS
...\...\src\CVS\Entries
...\...\...\...\Repository
...\...\...\...\Root
...\...\...\CVS
...\...\src
...\doc
...\rtl\CVS\Entries
...\...\...\Repository
...\...\...\Root
...\...\CVS
...\...\verilog\can_acf.v
...\...\.......\can_bsp.v
...\...\.......\can_btl.v
...\...\.......\can_crc.v
...\...\.......\can_defines.v
...\...\.......\can_fifo.v
...\...\.......\can_ibo.v
...\...\.......\can_register.v
...\...\.......\can_registers.v
...\...\.......\can_register_asyn.v
...\...\.......\can_register_asyn_syn.v
...\...\.......\can_register_syn.v
...\...\.......\can_top.v
...\...\.......\CVS\Entries
...\...\.......\...\Repository
...\...\.......\...\Root
...\...\.......\CVS
...\...\.......\README.txt
...\...\verilog
...\rtl
...\sim\CVS\Entries
...\...\...\Repository
...\...\...\Root
...\...\CVS
...\...\rtl_sim\bin\cds.lib
...\...\.......\...\CVS\Entries
...\...\.......\...\...\Repository
...\...\.......\...\...\Root
...\...\.......\...\CVS
...\...\.......\...\hdl.var
...\...\.......\...\INCA_libs\CVS\Entries
...\...\.......\...\.........\...\Repository
...\...\.......\...\.........\...\Root
...\...\.......\...\.........\CVS
...\...\.......\...\.........\worklib\CVS\Entries
...\...\.......\...\.........\.......\...\Repository
...\...\.......\...\.........\.......\...\Root
...\...\.......\...\.........\.......\CVS
...\...\.......\...\.........\.......\dir_keeper
...\...\.......\...\.........\worklib
...\...\.......\...\INCA_libs
...\...\.......\...\memory_file_list
...\...\.......\...\rtl_file_list
...\...\.......\...\sim_file_list
...\...\.......\bin
...\...\.......\CVS\Entries
...\...\.......\...\Repository
...\...\.......\...\Root
...\...\.......\CVS
...\...\.......\log\CVS\Entries
...\...\.......\...\...\Repository
...\...\.......\...\...\Root
...\...\.......\...\CVS
...\...\.......\...\dir_keeper
...\...\.......\log
...\...\.......\out\CVS\Entries
...\...\.......\...\...\Repository
...\...\.......\...\...\Root
...\...\.......\...\CVS
...\...\.......\...\dir_keeper
...\...\.......\out
...\...\.......\run\clean
...\...\.......\...\CVS\Entries
...\...\.......\...\...\Repository
...\...\.......\...\...\Root
...\...\.......\...\CVS
...\...\.......\...\run_sim.scr
...\...\.......\...\wave.do
...\...\.......\run