文件名称:VectCPU_1s40_0_81_nov0208
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国外博士写向量处理机，是和NIOS处理器一起开发的，对这个的研究比较透彻，希望对大家有用-Most previous research into vector architectures has concentrated on supercomputing applications
and small enhancements to existing vector supercomputer implementations. This thesis expands the body of
vector research by examining designs appropriate for single-chip full-custom vector microprocessor implementations
targeting a much broader range of applications.
I present the design, implementation, and evaluation of T0 (Torrent-0): the first single-chip vector
microprocessor. T0 is a compact but highly parallel processor that can sustain over 24 operations per
cycle while issuing only a single 32-bit instruction per cycle. T0 demonstrates that vector architectures
are well suited to full-custom VLSI implementation and that they perform well on many multimedia and
human-machine interface tasks.
The remainder of the thesis contains proposals for future vector microprocessor designs. I show
that the most area-efficient vector register file designs have several banks with severa
and small enhancements to existing vector supercomputer implementations. This thesis expands the body of
vector research by examining designs appropriate for single-chip full-custom vector microprocessor implementations
targeting a much broader range of applications.
I present the design, implementation, and evaluation of T0 (Torrent-0): the first single-chip vector
microprocessor. T0 is a compact but highly parallel processor that can sustain over 24 operations per
cycle while issuing only a single 32-bit instruction per cycle. T0 demonstrates that vector architectures
are well suited to full-custom VLSI implementation and that they perform well on many multimedia and
human-machine interface tasks.
The remainder of the thesis contains proposals for future vector microprocessor designs. I show
that the most area-efficient vector register file designs have several banks with severa
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下载文件列表
reg_memory.mif
scalarcore.stp
VectCPU_sys.qip
VectCPU_sys.qpf
VectCPU_sys.qsf
VectCPU_sys.sdc
assembler
.........\README.txt
.........\src
.........\...\binutils
.........\...\........\gas
.........\...\........\...\config
.........\...\........\...\......\tc-nios2.c
.........\...\........\include
.........\...\........\.......\opcode
.........\...\........\.......\......\nios2.h
.........\...\........\opcodes
.........\...\........\.......\nios2-opc.c
.........\Test
.........\....\test.asm
.........\....\vector_testsuite_results.log
.........\....\vector_testsuite_results2.log
.........\....\vector_testsuite_results3.log
.........\....\vector_testsuite_results4.log
.........\....\vector_testsuite_results5(final).log
.........\....\v_assembler_test.s
.........\....\v_assembler_test_extracomma.s
.........\....\v_assembler_test_wrongreg.s
README.txt
VectCPU_sys.sopc
ip
..\utiie_cpu
..\.........\cb_generator.pl
..\.........\class.ptf
..\.........\hdl
..\.........\...\Adder_w_Comparator.v
..\.........\...\ALU_Logic.v
..\.........\...\Branch_Logic.v
..\.........\...\Control_Registers.v
..\.........\...\Control_Unit.v
..\.........\...\Datapath.v
..\.........\...\Decoder_Logic.v
..\.........\...\Instruction_Fetch_Unit.v
..\.........\...\Instr_Register.v
..\.........\...\isa_def.v
..\.........\...\Logic_Unit.v
..\.........\...\Memory_Address_Align.v
..\.........\...\Memory_Byteenable.v
..\.........\...\Memory_Data_In_Align.v
..\.........\...\Memory_Data_Out_Align.v
..\.........\...\Next_PC_Shifter_Selection.v
..\.........\...\OpA_Selection.v
..\.........\...\OpB_Imm_Selection.v
..\.........\...\Pipeline_Reg.v
..\.........\...\Pipeline_S2_Regs.v
..\.........\...\Pipeline_S3_Regs.v
..\.........\...\Predecode_Instruction.v
..\.........\...\Program_Counter.v
..\.........\...\Register_File.v
..\.........\...\Reg_Write_Addr_Mux.v
..\.........\...\Reg_Write_Data_Mux.v
..\.........\...\Reg_Write_Enable.v
..\.........\...\Shifter_Unit.v
..\.........\...\Stage_Four.v
..\.........\...\Stage_One.v
..\.........\...\Stage_Three.v
..\.........\...\Stage_Two.v
..\.........\...\UT_II_Economy_cpu.v
..\.........\mif
..\.........\...\decoder_memory.mif
..\.........\...\reg_memory.mif
..\.........\modelsim dat
..\.........\............\decoder_memory.dat
..\.........\............\reg_memory.dat
..\vectcpu.sdc
..\vect_cpu
..\........\gen_loadaddr_roms.m
..\........\hdl
..\........\...\altMultAccum.v
..\........\...\ALU.v
..\........\...\components.v
..\........\...\config_def.v
..\........\...\config_def_auto.v
..\........\...\define.v
..\........\...\flagunit.v
..\........\...\isa_def.v
..\........\...\lanemult_mf.v
..\........\...\loadAddrGenerator.v
..\........\...\loadstoreAddrCount.v
..\........\...\loadstoreController.v
..\........\...\lsu_wraddr_q.v
..\........\...\MACunit.v
..\........\...\mathmacros.v
..\........\...\memIF.v
..\........\...\memreadIF.v
..\........\...\memwriteIF.v
..\........\...\memxbar.v
..\........\...\mem_order_q.v
..\........\...\NElemRemainder_rom_init.v
..\........\...\NElemXfer_rom_init.v