文件名称:verilog_cordic_core
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A highly configurable 1st quadrant CORDIC core in verilog-Details
Name: verilog_cordic_core
Created: Sep 14, 2008
Updated: Aug 12, 2011
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download
Statistics: View
Other project properties
Category: Arithmetic core
Language: Verilog
Development status:
Additional info: Design done, FPGA proven
WishBone Compliant: No
License:
Descr iption
Name: verilog_cordic_core
Created: Sep 14, 2008
Updated: Aug 12, 2011
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download
Statistics: View
Other project properties
Category: Arithmetic core
Language: Verilog
Development status:
Additional info: Design done, FPGA proven
WishBone Compliant: No
License:
Descr iption
(系统自动生成,下载前可以参看下载内容)
下载文件列表
doc.txt
verilog_cordic_core\tags\rel_1\cordic.v
...................\....\.....\manual.pdf
...................\....\.....\tb_cordic.v
...................\.runk\cordic.v
...................\.....\manual.pdf
...................\.....\tb_cordic.v
...................\web_uploads\cordic.v
...................\...........\manual.pdf
...................\...........\tb_cordic.v
...................\tags\rel_1
...................\branches
...................\tags
...................\trunk
...................\web_uploads
verilog_cordic_core