文件名称:temp
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掌握时间一直是人们最基本的需求，而在快节奏的当今社会，时间更是一个很重要的工具。电子时钟是利用电子技术构成时钟功能的装置，与机械式时钟相比具有更高的准确性和直观性，且无机械装置，拥有更长的寿命，因此现在越来越得到广泛的使用。按照系统设计功能的要求，系统分为综合计时模块，数据调整模块，红外接收解码模块以及显示模块等4个模块，其中综合计时模块又包含7个子模块（年、月、日、星期、时、分、秒），每个子模块都具有预置，计数和进位的功能。(Time is always the basic need of people, and in the fast pace of today's society, time is a very important tool. The electronic clock is a clock device function by using electronic technology, compared with the mechanical clock has a higher accuracy and intuitive, and no mechanical device, has a longer life, so it is more and more widely used. According to the system design requirements, the system is divided into comprehensive timing module, data adjustment module, infrared receiving module and display module of 4 modules, including the timing module includes 7 sub modules (year, month, day, week, hours, minutes and seconds), each module has a preset counting and carry the function.)
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下载文件列表
temp
temp\.Xil
temp\.Xil\Vivado-11748-DESKTOP-1URT7V0
temp\.Xil\Vivado-11748-DESKTOP-1URT7V0\wave
temp\.Xil\Vivado-16156-DESKTOP-1URT7V0
temp\.Xil\Vivado-16156-DESKTOP-1URT7V0\wave
temp\.Xil\Vivado-17180-DESKTOP-1URT7V0
temp\.Xil\Vivado-17180-DESKTOP-1URT7V0\wave
temp\temp.cache
temp\temp.cache\compile_simlib
temp\temp.cache\compile_simlib\activehdl
temp\temp.cache\compile_simlib\ies
temp\temp.cache\compile_simlib\modelsim
temp\temp.cache\compile_simlib\questa
temp\temp.cache\compile_simlib\riviera
temp\temp.cache\compile_simlib\vcs
temp\temp.cache\wt
temp\temp.cache\wt\gui_resources.wdf
temp\temp.cache\wt\java_command_handlers.wdf
temp\temp.cache\wt\project.wpc
temp\temp.cache\wt\synthesis.wdf
temp\temp.cache\wt\synthesis_details.wdf
temp\temp.cache\wt\webtalk_pa.xml
temp\temp.cache\wt\xsim.wdf
temp\temp.hw
temp\temp.hw\hw_1
temp\temp.hw\hw_1\hw.xml
temp\temp.hw\hw_1\wave
temp\temp.hw\temp.lpr
temp\temp.ip_user_files
temp\temp.ip_user_files\README.txt
temp\temp.ip_user_files\ip
temp\temp.ip_user_files\ip\clk_wiz_0
temp\temp.ip_user_files\ip\clk_wiz_0\clk_wiz_0.veo
temp\temp.ip_user_files\ip\clk_wiz_1
temp\temp.ip_user_files\ip\clk_wiz_1\clk_wiz_1.veo
temp\temp.ip_user_files\ipstatic
temp\temp.ip_user_files\ipstatic\clk_wiz_v5_3_1
temp\temp.ip_user_files\ipstatic\clk_wiz_v5_3_1\mmcm_pll_drp_func_7s_mmcm.vh
temp\temp.ip_user_files\ipstatic\clk_wiz_v5_3_1\mmcm_pll_drp_func_7s_pll.vh
temp\temp.ip_user_files\ipstatic\clk_wiz_v5_3_1\mmcm_pll_drp_func_us_mmcm.vh
temp\temp.ip_user_files\ipstatic\clk_wiz_v5_3_1\mmcm_pll_drp_func_us_pll.vh
temp\temp.ip_user_files\sim_scripts
temp\temp.ip_user_files\sim_scripts\clk_wiz_0
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\README.txt
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\activehdl
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\activehdl\README.txt
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\activehdl\clk_wiz_0.sh
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\activehdl\clk_wiz_0.udo
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\activehdl\compile.do
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\activehdl\file_info.txt
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\activehdl\glbl.v
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temp\temp.ip_user_files\sim_scripts\clk_wiz_0\ies
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\ies\README.txt
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\ies\clk_wiz_0.sh
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\ies\file_info.txt
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\ies\glbl.v
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\ies\run.f
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\modelsim
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\modelsim\README.txt
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\modelsim\clk_wiz_0.sh
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\modelsim\clk_wiz_0.udo
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\modelsim\compile.do
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\modelsim\file_info.txt
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\modelsim\glbl.v
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\modelsim\simulate.do
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\modelsim\wave.do
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\questa
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\questa\README.txt
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\questa\clk_wiz_0.sh
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\questa\clk_wiz_0.udo
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\questa\compile.do
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\questa\elaborate.do
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\questa\file_info.txt
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\questa\glbl.v
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temp\temp.ip_user_files\sim_scripts\clk_wiz_0\questa\wave.do
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\riviera
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\riviera\README.txt
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\riviera\clk_wiz_0.sh
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\riviera\clk_wiz_0.udo
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\riviera\compile.do
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\riviera\file_info.txt
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\riviera\glbl.v
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\riviera\simulate.do
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temp\temp.ip_user_files\sim_scripts\clk_wiz_0\vcs
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\vcs\README.txt
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\vcs\clk_wiz_0.sh
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temp\temp.ip_user_files\sim_scripts\clk_wiz_0\vcs\glbl.v
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temp\temp.ip_user_files\sim_scripts\clk_wiz_0\xsim
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temp\temp.ip_user_files\sim_scripts\clk_wiz_0\xsim\clk_wiz_0.sh
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\xsim\cmd.tcl
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\xsim\elab.opt
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\xsim\file_info.txt
temp\.Xil
temp\.Xil\Vivado-11748-DESKTOP-1URT7V0
temp\.Xil\Vivado-11748-DESKTOP-1URT7V0\wave
temp\.Xil\Vivado-16156-DESKTOP-1URT7V0
temp\.Xil\Vivado-16156-DESKTOP-1URT7V0\wave
temp\.Xil\Vivado-17180-DESKTOP-1URT7V0
temp\.Xil\Vivado-17180-DESKTOP-1URT7V0\wave
temp\temp.cache
temp\temp.cache\compile_simlib
temp\temp.cache\compile_simlib\activehdl
temp\temp.cache\compile_simlib\ies
temp\temp.cache\compile_simlib\modelsim
temp\temp.cache\compile_simlib\questa
temp\temp.cache\compile_simlib\riviera
temp\temp.cache\compile_simlib\vcs
temp\temp.cache\wt
temp\temp.cache\wt\gui_resources.wdf
temp\temp.cache\wt\java_command_handlers.wdf
temp\temp.cache\wt\project.wpc
temp\temp.cache\wt\synthesis.wdf
temp\temp.cache\wt\synthesis_details.wdf
temp\temp.cache\wt\webtalk_pa.xml
temp\temp.cache\wt\xsim.wdf
temp\temp.hw
temp\temp.hw\hw_1
temp\temp.hw\hw_1\hw.xml
temp\temp.hw\hw_1\wave
temp\temp.hw\temp.lpr
temp\temp.ip_user_files
temp\temp.ip_user_files\README.txt
temp\temp.ip_user_files\ip
temp\temp.ip_user_files\ip\clk_wiz_0
temp\temp.ip_user_files\ip\clk_wiz_0\clk_wiz_0.veo
temp\temp.ip_user_files\ip\clk_wiz_1
temp\temp.ip_user_files\ip\clk_wiz_1\clk_wiz_1.veo
temp\temp.ip_user_files\ipstatic
temp\temp.ip_user_files\ipstatic\clk_wiz_v5_3_1
temp\temp.ip_user_files\ipstatic\clk_wiz_v5_3_1\mmcm_pll_drp_func_7s_mmcm.vh
temp\temp.ip_user_files\ipstatic\clk_wiz_v5_3_1\mmcm_pll_drp_func_7s_pll.vh
temp\temp.ip_user_files\ipstatic\clk_wiz_v5_3_1\mmcm_pll_drp_func_us_mmcm.vh
temp\temp.ip_user_files\ipstatic\clk_wiz_v5_3_1\mmcm_pll_drp_func_us_pll.vh
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temp\temp.ip_user_files\sim_scripts\clk_wiz_0
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\README.txt
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\activehdl
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\activehdl\README.txt
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\activehdl\clk_wiz_0.sh
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\activehdl\clk_wiz_0.udo
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temp\temp.ip_user_files\sim_scripts\clk_wiz_0\activehdl\file_info.txt
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\activehdl\glbl.v
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\activehdl\simulate.do
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\activehdl\wave.do
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temp\temp.ip_user_files\sim_scripts\clk_wiz_0\ies\clk_wiz_0.sh
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\ies\file_info.txt
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temp\temp.ip_user_files\sim_scripts\clk_wiz_0\ies\run.f
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\modelsim
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\modelsim\README.txt
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\modelsim\clk_wiz_0.sh
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\modelsim\clk_wiz_0.udo
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\modelsim\compile.do
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\modelsim\file_info.txt
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temp\temp.ip_user_files\sim_scripts\clk_wiz_0\modelsim\simulate.do
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\modelsim\wave.do
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\questa
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\questa\README.txt
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\questa\clk_wiz_0.sh
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\questa\clk_wiz_0.udo
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\questa\compile.do
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temp\temp.ip_user_files\sim_scripts\clk_wiz_0\questa\file_info.txt
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temp\temp.ip_user_files\sim_scripts\clk_wiz_0\questa\wave.do
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\riviera
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\riviera\README.txt
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\riviera\clk_wiz_0.sh
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\riviera\clk_wiz_0.udo
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\riviera\compile.do
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temp\temp.ip_user_files\sim_scripts\clk_wiz_0\vcs
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temp\temp.ip_user_files\sim_scripts\clk_wiz_0\vcs\clk_wiz_0.sh
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temp\temp.ip_user_files\sim_scripts\clk_wiz_0\xsim\clk_wiz_0.sh
temp\temp.ip_user_files\sim_scripts\clk_wiz_0\xsim\cmd.tcl
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temp\temp.ip_user_files\sim_scripts\clk_wiz_0\xsim\file_info.txt