文件名称:Verilog的边沿检测技术_设计源代码

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • 上传时间:
  • 2018-03-01
  • 文件大小:
  • 36kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • gxg***
  • 相关连接:
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波形数据上升下降沿的检测程序,已经经过仿真验证(The detection program of the rising descending edge of the waveform data has been verified by simulation)
相关搜索: verilog
fpga

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下载文件列表

文件名大小更新时间
edge_tech_design\edge_tech_design.asm.rpt 8625 2011-06-25
edge_tech_design\edge_tech_design.done 26 2011-06-25
edge_tech_design\edge_tech_design.fit.rpt 89331 2011-06-25
edge_tech_design\edge_tech_design.fit.smsg 513 2011-06-25
edge_tech_design\edge_tech_design.fit.summary 612 2011-06-25
edge_tech_design\edge_tech_design.flow.rpt 7448 2011-06-25
edge_tech_design\edge_tech_design.map.rpt 20191 2011-06-25
edge_tech_design\edge_tech_design.map.summary 470 2011-06-25
edge_tech_design\edge_tech_design.pin 27099 2011-06-25
edge_tech_design\edge_tech_design.pof 524475 2011-06-25
edge_tech_design\edge_tech_design.qpf 1272 2011-06-25
edge_tech_design\edge_tech_design.qsf 2860 2011-06-25
edge_tech_design\edge_tech_design.sof 240776 2011-06-25
edge_tech_design\edge_tech_design.sta.rpt 30691 2011-06-25
edge_tech_design\edge_tech_design.sta.summary 639 2011-06-25
edge_tech_design\src\edge_tech_block.bdf 11918 2011-06-25
edge_tech_design\src\edge_tech_design.v 871 2011-06-25
edge_tech_design\src\edge_tech_design.v.bak 0 2011-06-25
edge_tech_design\src 0 2011-09-09
edge_tech_design 0 2011-09-09

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