搜索资源列表
SDRAM
- 连接Nios II 和SDRAM的系统设计，DDR SDRAM设计及调试经验总结，MT48LC16M16资料。-failed to translate
S5PC100_UM_REV1.04
- Samsung s new ARM cpu datasheet. S5PC100 Spec. - CPU ARM Cortex-A8 667-833Mhz - 32KB L1, 256KB L2 Cache - Video 720p (1280x720 Play. h.264 divx, mp4...) - nand, sd/mmc, usb booting - Windows CE 6.0, Linux (*
ddr
- 测试DDR内存，Linux下编译运行-Test Demos under CCS\tests\ddr
DDR_prj
- DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA。-DDR controller VHDL source code. FPGA implementation using DDR interface controller for Altera' s FPGA.
DDRSDRAM_MT46V32M16TG
- ddr控制器 对DDR实现读写控制-ddr control
DDRcontroller
- 对DDR控制器的FPGA实现及其代码和参考注释-verilog source code written to read and write DDR
DDRdesigen.pdf
- DDR SDRAM设计及调试经验总结.pdf-DDR SDRAM design and debug Experience. Pdf
DDR_SDRAMDesignTutorials
- Altera公司的基于NIOSII设计DDR和DDR2内存的资料，很有帮助的，-Based on Altera' s DDR and DDR2 memory NIOSII design information, useful,
DDR
- HYB25025616的IP核，可直接用于microblaze的应用里，在合众达FEM024板子直接使用-HYB25025616 the IP core, can be used directly microblaze application, the board in the Triangle over FEM024 directly
Magnetic
- 磁珠专用于抑制信号线、电源线上的高频噪声和尖峰干扰，还具有吸收静电脉冲的能力。磁珠是用来吸收超高频信号，像一些RF电路，PLL，振荡电路，含超高频存储器电路（DDR SDRAM，RAMBUS等）都需要在电源输入部分加磁珠，而电感是一种蓄能元件，用在LC振荡电路，中低频的滤波电路等，其应用频率范围很少超过50MHZ。-Inhibition of signal lines dedicated to beads, the power line
ref-ddr-sdram-verilog
- ddr_sdram开发参考verilog建模-ddr_sdram with verilog
ddr_code
- 基于FPGA的DDR SDRAM控制器的VHDL硬件描述语言-FPGA-based DDR SDRAM controller VHDL hardware descr iption language
ddr
- DM6446 ddr ccs 仿真器测试程序-DM6446 ddr program in CCS
DX-PHY
- ddr phy design spec and example-ddr phy design spec and example!!
omap3530
- omap3530的datasheet，OMAP3530集成ARM+DSP+3D,ARM部分主频达到600MHZ，DSP采用430-MHz TMS320C64x+™ DSP Core，DDR可从128MB扩展到512M，尺寸基于7寸数字屏，主板由核心板和底板构成-omap3530 the datasheet, OMAP3530 integrates ARM+ DSP+3 D, ARM parts of speeds up to
ddr_sdr_V1_1
- its the vhdl stuff for ddr sdram controller nice one easily understandable-its the vhdl stuff for ddr sdram controller nice one easily understandable
sdram_controller_latest.tar
- sdram_controller_latest.tar.gz -it is memory DDR controller, but it has 8 bit only data bus wide ,and hasn’t independents clock for source read-write data and ddr + controller size. Wrote on the VHDL language.-sdram_cont
S3C6410_core_sch
- ok6410最新核心板最小系统原理图，包含mobile ddr， nandflash-ok6410 latest minimum system schematic core board, including mobile ddr, nandflash
Hardware_and_Layout_Design_Considerations_for_DDR_
- DDR SDRAM接口的硬件和布线设计指南。DDR SDRAM的传输速度越来越高，对走线的要求也越来越高。-DDR SDRAM HARDWARE LAYOUT DESIGN
DDR_SDRAM_design_and_conclusion
- DDR SDRAM总结文档，描述了DDR IP的设计挑战，接口时序，模块设计原则，调试技巧及应用指南-DDR SDRAM summary document describing the design challenge of DDR IP, interface timing, modular design principles, debugging skills and Application Guide