搜索资源列表
ddr
- linux 下的bootloader中的内存的裸板驱动程序-the driver of ddr in the bootloader
DDR-SDRAM
- ddr sdram 控制器的源代码，内有vhdl和verilog。-DDR SDRAM controller
treff-ddr-sdrh
- 本程序源码是DDR SDRAM控制器的VHDL程序源源码，由ALTERA 提供 -The program source code is DDR SDRAM controller VHDL source source code provided by ALTERA
ddr
- 达芬奇DM6446的ddr驱动程序，已经测试可以使用 -The DaVinci DM6446 ddr driver has been tested can be used
ddr-sdram
- It is complete document for DDR SD RAM program in verilog hdl
DDR-SDRAM-controller-verilog-code
- DDR SDRAM控制器verilog代码及中文说明文档-DDR SDRAM controller verilog code and documentation
ddr
- C6474上的DDR测试程序，测试环境为CCS3.3,对DSP编程的新手有一定的帮助-The DDR testing program in C6474, using CCS3.3 environment. And it s helpful for starter of DSP programming.
ddr-sdram-control
- ddr sdram控制器的设计与验证，提供了一种极为可靠且简易的控制器设计方案。-DDR SDRAM controller design and verification, providing an extremely reliable and simple controller design.
DDR-SDRAM-design-and-debugging
- DDR SDRAM设计及调试经验总结 DDR SDRAM设计及调试经验总结-DDR SDRAM design and debugging Experience
ddr
- 德州仪器公司的DM6437DSP内存测试程序，用于检测DSP能否正常工作，尤其是初始化阶段。-it s a program of DM6437 DSP DDR testing designed by TI Company. Using it to test whether the DSP is functioning well, especially at beginning.
ddr
- DDR 布线规则,pcb工程师应该多学习-DDR routing rules, pcb engineers should study more
DM365-ddr-test-and-debug-programs
- DM365的ddr测试和板子调试程序，最后调试顺利通过-DM365 ddr test and debug programs and at last successful
verilog-ddr-sdram
- 用verilog实现的ddr sdram控制器-ddr sdram by verilog hdl
10.ddr
- tiny6410 linux系统下ddr驱动程序-Under tiny6410 linux system ddr driver
ddr
- tiny210 s5pv210 DDR初始化-tiny210 s5pv210 DDR initialization
ddr
- this file contain sources code for ddr sdram
ddr
- 达芬奇系列开发板，ddr测试程序，用于检测Dsp和ddr之间的通路正常工作-Da Vinci series development board, DDR test program, used to detect between Dsp and DDR pathways to work normally
ddr
- Definitions for the DDR registers.
ddr
- S3C6410的DDR驱动程序，实现了对DDR的读写操作-S3C6410 of DDR drivers, the realization of DDR read and write operations
DDR-SDRAM-Controller
- DDR SDRAM控制器verilog代码及中文说明文档-DDR SDRAM Controller Using Virtex-5 FPGA Devices