搜索资源列表
pll
- 用FPGA实现数字锁相环，开发环境为ISE-Using FPGA digital phase-locked loop, development environment for ISE
fir_16
- fir低通滤波器 用于dspbuilder pll：25ns data 400khz sin 10.8khz-fir low-pass filter for dspbuilder pll: 25ns data 400khz sin 10.8khz
FractionalPLLDesign
- 是关于sigma delta PLL设计的详细论文，论文中有具体的设计细节，并在附录中有相应的matlab、vhdl code-Is about the design of sigma delta PLL detailed papers, papers in the specific design details, and in the appendix corresponding matlab, vhdl code
pll_component_design_matlab
- PLL system LPF/PFD/VCO/Divider model in Matlab,在Matlab中将PLL系统的各个模块模型话，便于分析整个PLL的环路稳定特性，锁定时间等…… 附录中包含完整的Matlab code-PLL system LPF/PFD/VCO/Divider model in Matlab, the Matlab will PLL system model of each module, the easy
costas_loop
- 使用改进的COSTAS环实现锁相环（PLL），应用于高动态的数字化接收系统-COSTAS Central improved to achieve phase-locked loop (PLL), used in high dynamic digital reception system
MHPerrottPhDThesis
- Ph.D thesis from M.H.Perrott, about Fractional-N PLL design.
clock_system_of_LPC23xx
- LPC23xx系列ARM时钟源的选择、PLL的设置步骤以及注意事项等。PPT做的非常出色。-LPC23xx Series ARM clock source selection, PLL settings, as well as attention to matters such as these. PPT doing very well.
formatter
- Actel 基本VHDl模块源代码，包括BCD、LCD、PLL等-Actel basic VHDL source code modules, including BCD, LCD, PLL, etc.
MC145152
- 1、数字锁相环的单片机代码。 2、单片机与数字锁相环MC145152的应用系统的设计与实现。-1, the single-chip digital phase-locked loop code. 2, microcontroller and digital PLL MC145152 Application System Design and Implementation.
DE2_VGA3
- The VGA example generates a 320x240 diffusion-limited-aggregation (DLA) on Altera DE2 board. A DLA is a clump formed by sticky particles adhering to an existing structure. In this design, we start with one pixel at the c
pll
- 收集的数字锁相环设计相关文章多篇.主要采用VHDL语言进行设计.-Collection of digital phase-locked loop design articles related articles. Mainly VHDL design languages.
DSP_C_Function
- 转载自Rulph Chassaing的源代码,内有函数Adaptc,AdaptIDFIR,adaptidFIRw,AdaptIDIIR, Adaptnoise,Adaptnoise_pcm,Adaptpredict, Adaptpredict_pcm,Aliasing,AM,DFT,Dotp4, dotp4clasm,Dotpintrinsic,Dotpipedfix, Dotpnp,Echo_control,Factc
TEA5767_C51
- 用到飞利浦的TEA5767的收音机模块,SP3767和TEA5767完全兼容 TEA5767采用I2C或者三线接口控制,我是用的I2C,单片机用STC89C52,带1K EEPROM,可以掉电存台,1602LCD显示,这里只给了TEA5767的控制程序, TEA5767读写数据都是5个字节,其中PLL参数14位.-Philips TEA5767 use of the radio module, SP3767 and TEA
fq_div
- pll 的64倍频 锁相环技术用 实现倍频 从而达到对频率的分频-pll 64 multiplier PLL multiplier used to achieve so as to achieve the sub-band of frequencies
PhaseNoise
- 小数分频技术解决了锁相环频率合成器中的频率分辨率和转换时间的矛盾, 但是却引入了严重的相位噪声, 传统的相位补偿方法由于对Aö D 等数字器件的要求很高并具有滞后性实现难度较大。$2 调制器对噪声具有整形的功 能, 因而将多阶的$2 调制器用于小数分频合成器中可以很好地解决他的相位噪声的问题, 大大促进了小数分频技术的 发展和应用。文章最后给出了在GHz 量级上实现的这种新型小数分频合成器的应用电路, 并测得良好的相
111
- 数字鉴相器,数字锁相环频率合成系统FPGA的实现,很有借鉴价值-Digital phase detector, digital PLL frequency synthesizer system FPGA realization of referential value
dds_new
- 驱动时钟加入了PLL,使得DDS的驱动时钟可变.32位的NCO使得DDS的分辨率可以做到Hz量级-Clock driver joined the PLL, the DDS makes the clock-driven variable-.32-bit NCO makes the resolution of DDS can be done Hz magnitude
4154
- PLL芯片ATF4154控制程序，单片机，51，调试通过了的，可以使用-ATF4154 chip PLL control procedures, single-chip, 51, has been endorsed by the debugger, you can use
Aidio
- 摘要：应用CXA1019S芯片完成接收机混频、中放、解调等的设计，并用芯片BU2614以PLL 频率合成的方法产生稳定的本振和控制输入调谐回路的谐振频率，从而实现电调谐。单片机采用 MCS-51系列对频率合成器BU2614进行控制，加上键盘、显示和存储器电路，可实现多种程控搜 索、电台存储等功能。-Abstract: The complete receiver chip CXA1019S mixer, amplifier,
vga_timing
- 此乃VGA驱动的详细源码，并配有PLL。使用Quartus II 开发。-This is a detailed source VGA driver with a PLL. Use Quartus II development.