搜索资源列表
ahb_arb_def
- ahb arbiterdefine 文件-ahb arbiterdefine
ahb_decode
- ahb decoder 文件，主要描述ahbdecoder-ahb decoder file
ahb_master
- ahb master 文件，主要是ahb发数据-ahb master file
ahb_slave
- 主要是用来描述的ahb slave的文件-ahb slave file
ahb_slave_latest.tar
- ahb protocol descr iption and its implementation using verilog -ahb protocol descr iption and its implementation using verilog
ADC3andDMAhighspeed(2.4Msps)
- 硬件平台：STM32F429I-DISCORVERY 软件平台：KEIL MDK5.10 在STM32F429I-DISCO board中，由于串口2被L3GD20和液晶数据线占用，所以串口1很方便，而且还留了2个孔外接。 * 说 明 : 实现printf和scanf函数重定向到串口1，即支持printf信息到USART1 * 实现重定向，只需要添加2个函数: * int fputc(int ch,
ahb_system_generator_latest.tar
- AHB system generator. This file is a part of a system generator for AHB system. it is VHDL code for the AMBA arbiter.
ahb_slave
- 异步memory ahb lite slave接口verilog代码-verilog code of ahb lite slave for memory interface
slave_ahb1988
- slave ahb 1988 verilog
slave-control
- ahb_slave control to introduce ahb
ahb_bus
- ahb总线代码,现支持4个master，可扩展-ahb bus verilog module
ahb_verilog_design
- 代码为ahb interface ，用verilog编写的,包括仿真和综合。-Code for the interface AHB, written in Verilog, including simulation and synthesis.
bus_ahb_to_sram
- amba ahb to sram verilog
verilog
- AHB BUS, Master Slave Arbiter,AHB System是由Master，Slave，Infrastructure 三部分所组成。-example-AHB BUS, Master Slave Arbiter
AMBA
- AMBA总线的Verilog语言模型，主要包括5个部分：AHB总线仲裁器，AHB-APB总线桥接器，AHB总线上从设备ROM模型-AMBA bus of ARM company, It mainly includes the following five parts: the AHB arbiter,AHB-APB bridge, AHB_Rom_Slave, AHB_Ram_Slave
APB_Servo_code_final
- test code by verilogHDL. SERVO MOTER operation code at FPGA. AHB and APB BUS Architecture.
abma
- Verilog/VHDL AHB AMBA BUS Arch.
ahb_ebc
- Sipmle external bus controller realization on Verilog HDL with AHB interface. Support RAM/ROM/NAND Flash devices.
ahb_i2c
- AHB TO I2C转换代码 实现ahb2ic转换(command ahb to i2c brige and you can work with it)
CCIR656Detect
- ccir 656信号的detect 和转换过程详细介绍(command ahb to i2c brige and you can work with it)