[其他嵌入式/单片机内容] main

说明：TI公司的ZigBee模块 cc2530单片机带屏基础实验---LCD-test-TI ZigBee module CC2530 chip with screen based experiment--- LCD-test
<俞建> 在 2025-06-16 上传 | 大小：1kb | 下载：0

[其他嵌入式/单片机内容] 12864chuan-xing-yan-shi

说明：12864串行演示资料含有源码硬件电路通过-12864 Serial Presentation by hardware circuits with source
<王子片> 在 2025-06-16 上传 | 大小：15kb | 下载：0

[单片机(51,AVR,MSP430等)] 12864tu-wen-ce-shi

说明：基于单片机的12864图文显示，已通过硬件验证-12864-based single-chip graphic display, has been verified by hardware
<王子片> 在 2025-06-16 上传 | 大小：35kb | 下载：0

[VHDL编程] Chapter-1

说明：Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are
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[VHDL编程] Chapter-2

说明：Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are
<shixiaodong> 在 2025-06-16 上传 | 大小：5kb | 下载：0

[VHDL编程] Chapter-3

说明：Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are
<shixiaodong> 在 2025-06-16 上传 | 大小：4kb | 下载：0

[VHDL编程] Chapter-4

说明：Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are
<shixiaodong> 在 2025-06-16 上传 | 大小：7kb | 下载：0

[VHDL编程] Chapter-5

说明：Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are
<shixiaodong> 在 2025-06-16 上传 | 大小：15kb | 下载：0

[VHDL编程] 2DPSK

说明：vhdl,Digital phase modulation is also known as phase shift keying, 2DPSK is binary differential phase shift keying, is a kind of digital phase modulation. Digital phase modulation using carrier phase change to transmit digital signal, usually can be
<乐逍遥> 在 2025-06-16 上传 | 大小：1.82mb | 下载：0

[VHDL编程] Chapter-6

说明：练习六在verilog hdl中使用函数317 -• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed on
<shixiaodong> 在 2025-06-16 上传 | 大小：3kb | 下载：0

[VHDL编程] Chapter-7

说明：练习七在verilog hdl中使用任务（task）319 -• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are program
<shixiaodong> 在 2025-06-16 上传 | 大小：7kb | 下载：0

[VHDL编程] Chapter-8

说明：练习八利用有限状态机进行时序逻辑的设计322 -• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed on
<shixiaodong> 在 2025-06-16 上传 | 大小：328kb | 下载：0