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[VHDL编程I2C_vhdl

说明: IMPORTANT NOTE: This design uses the I2C SCL signal as a clock. This requires that the SCL signal have clean, fast edges on both the rising and falling edges of this signal. Slow rise and fall times on this signal can show noise effects whic
<vijendra pal> 在 2025-06-20 上传 | 大小:830kb | 下载:0

[VHDL编程manchester_verilog

说明: This design is targeted to the XCR3064XL-7VQ100C CoolRunner CPLD. This is a 3V, 64 macrocell device in a 100 VQFP package. The fitter was allowed to pick the pin-out for the device.
<vijendra pal> 在 2025-06-20 上传 | 大小:10kb | 下载:0

[VHDL编程manchester_vhdl

说明:This design is targeted to the XCR3064XL-7VQ100C CoolRunner CPLD. This is a 3V, 64 macrocell device in a 100 VQFP package. The fitter was allowed to pick the pin-out for the device.
<vijendra pal> 在 2025-06-20 上传 | 大小:11kb | 下载:0

[VHDL编程spi_cpld_vhdl

说明:The CoolRunner-II "Confuguring Xilinx FPGAs with SPI Flash Memories using CoolRunner-II CPLDs" reference design is based upon the STMicroelectronics SPI Flash memory M25P20. This design can be easily modified to support other families of S
<vijendra pal> 在 2025-06-20 上传 | 大小:431kb | 下载:0

[VHDL编程uart_verilog

说明:The UART design was designed from a standard uart function with a read/write microprocessor interface. It includes standard framing error, parity control and overrun detection. This design is targeted to the XCR3128XL-7VQ100C CoolRunner CPLD. This
<vijendra pal> 在 2025-06-20 上传 | 大小:5kb | 下载:0

[VHDL编程uart_vhdl

说明:The UART design was designed from a standard uart function with a read/write microprocessor interface. It includes standard framing error, parity control and overrun detection. This design is targeted to the XCR3128XL-7VQ100C CoolRunner CPLD. This
<vijendra pal> 在 2025-06-20 上传 | 大小:6kb | 下载:0

[VHDL编程smartcard_vhdl

说明:Readme File for Smart Card Reader File Contents ************************************************************************* This zip file contains the following files: -- VHDL Source Files in Smartcard: Top.vhd - top level file for Pic
<vijendra pal> 在 2025-06-20 上传 | 大小:515kb | 下载:0

[VHDL编程project-05

说明:Project05.zip Memory.hdl
<Rosh> 在 2025-06-20 上传 | 大小:13kb | 下载:0

[DSP编程21k_asm

说明:analog device ADSP developement tools and descr iption 1
<fau> 在 2025-06-20 上传 | 大小:421kb | 下载:0

[DSP编程21k_ccm

说明:analog device ADSP developement tools and descr iption for AD21-analog device ADSP developement tools and descr iption for AD21xx
<fau> 在 2025-06-20 上传 | 大小:2.04mb | 下载:0

[DSP编程21xx_gsg(wb)

说明:analog device ADSP developement tools and descr iption - various
<fau> 在 2025-06-20 上传 | 大小:562kb | 下载:0

[DSP编程160isref

说明:analog device ADSP developement tools and descr iption for programmers
<fau> 在 2025-06-20 上传 | 大小:1.08mb | 下载:0
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