资源列表
[微处理器(ARM/PowerPC等)] 2440test
说明:QQ2440的测试代码,采用ADS开发的,还可以-QQ2440 testing code, the use of ADS development can also be<黄小林> 在 2025-06-18 上传 | 大小:4.1mb | 下载:0
[单片机(51,AVR,MSP430等)] Rapid_Modelling_for_Increasing
说明:Rapid Modelling is based on queuing theory but other mathematical modelling techniques as well as simulation models to facilitate the transfer of knowledge from theory to application are of interest in this context as well.<jomata63> 在 2025-06-18 上传 | 大小:4.1mb | 下载:0
[VHDL编程] ucosII_fpga
说明:ucos 在xilinx FPGA上的移植代码和bsp编写工程-This is a xilinx FPGA ucos and bsp source<qinjian> 在 2025-06-18 上传 | 大小:4.1mb | 下载:0
[其他嵌入式/单片机内容] ThefinalGbdoc
说明:About to control green house effect-About to control green house effect...<andyanand> 在 2025-06-18 上传 | 大小:4.1mb | 下载:0
[单片机(51,AVR,MSP430等)] SOC
说明:soc课件soc的发展趋势 soc 系统-courseware development trend of soc soc soc systems<尚国辉> 在 2025-06-18 上传 | 大小:4.1mb | 下载:0
[uCOS开发] exampleucosiiprogram
说明:ucosii网络通信开发例程,以周立功开发模版为基础,自行开发UCOSii下tcp测试代码- this is for ucosii and tcp test<张松波> 在 2025-06-18 上传 | 大小:4.1mb | 下载:0
[VHDL编程] Verilog
说明:基于Quartus II 9.0 (32-Bit)的Verilog语言时钟程序,五个独立按键分别可调十分秒的加减和确定,此程序通过硬件调试成功。-Based on Quartus II 9.0 (32-Bit) of the Verilog language, clock, five independent second key addition and subtraction, respectively, is adjustable and determined the success of<曾斌> 在 2025-06-18 上传 | 大小:4.1mb | 下载:0
[VHDL编程] 22FINAL_24
说明:System will automatically delete the directory of debug and release, so please do not put files on these two directory.<Qiu yunliang> 在 2025-06-18 上传 | 大小:4.1mb | 下载:0
[Windows CE] sqlite_wince
说明:SQLite非常著名的嵌入式数据库,可以跨平台,在VS2005+WINCE编译通过-Very famous SQLite embedded database, cross-platform, VS2005+WINCE compiled by<海涛> 在 2025-06-18 上传 | 大小:4.1mb | 下载:0