资源列表
[VHDL编程] Butterfly_lovers_beef
说明:verilog编写的蜂鸣器音乐《梁山伯与祝英台》。系统时钟为50MHz。-Verilog prepared buzzer music Butterfly Lovers . The system clock is 50MHz.<刘宇洋> 在 2025-05-24 上传 | 大小:1kb | 下载:0
[VHDL编程] async_fifo
说明:用verilog编写的简单异步fifo。可以给初学者用来学习fifo的初步工作原理。(不能直接使用。)-Verilog prepared by the simple asynchronous fifo. Can be used for beginners to learn fifo the initial working principle. (Can not be used directly.)<刘宇洋> 在 2025-05-24 上传 | 大小:1kb | 下载:0
[VHDL编程] pwm_generate_module
说明:verilog编写的,用按键控制PWM波占空比。可以定义死区,用来控制舵机或者led灯的亮暗。-Verilog prepared, with the button to control the PWM wave duty cycle. You can define the dead zone, used to control the steering gear or led lights bright and dark.<刘宇洋> 在 2025-05-24 上传 | 大小:1kb | 下载:0
[其他嵌入式/单片机内容] ADC_of_MSP430F249
说明:A single sample is made on A10 with reference to internal 1.5V Vref. Software sets ADC12SC to start sample and conversion - ADC12SC automatically cleared at EOC. ADC12 internal oscillator times sample and conversio<sattarhastam> 在 2025-05-24 上传 | 大小:1kb | 下载:0
[其他嵌入式/单片机内容] TimerA_of_MSPF249
说明:Toggle P1.0 using software and the TA_0 ISR. Timer_A is configured for up mode, thus the timer overflows when TAR counts to CCR0. In this example, CCR0 is loaded with 1000-1. ACLK = TACLK = INCLK = 32768Hz, MCLK =<sattarhastam> 在 2025-05-24 上传 | 大小:1kb | 下载:0
[其他嵌入式/单片机内容] I2C_of_MSP430F249
说明:This demo connects two MSP430 s via the I2C bus. The master reads 5 bytes the slave. This is the MASTER CODE. The data the slave transmitter begins at 0 and increments with each transfer. The USCI_B0 RX interrupt i<sattarhastam> 在 2025-05-24 上传 | 大小:1kb | 下载:0
[其他嵌入式/单片机内容] SPI_of_MSP430F249
说明: SPI master talks to SPI slave using 3-wire mode. Incrementing data is sent by the master starting at 0x01. Received data is expected to be same as the previous transmission TXData = RXData-1. USCI RX ISR is use<sattarhastam> 在 2025-05-24 上传 | 大小:1kb | 下载:0
[其他嵌入式/单片机内容] UART_of_MSP430F249
说明: Echo a received character, RX ISR used. Normal mode is LPM0. USCI_A0 RX interrupt triggers TX Echo. Baud rate divider with 1MHz = 1MHz/19200 = ~52.1 ACLK = n/a, MCLK = SMCLK = CALxxx_1MHZ = 1MHz<sattarhastam> 在 2025-05-24 上传 | 大小:1kb | 下载:0
[其他嵌入式/单片机内容] FLASH_WRITE_of_MSP430
说明: This program first erases flash seg C, then it increments all values in seg C, then it erases seg D, then copies seg C to seg D. Seg C @ 1040h Seg D @ 1000h The EEI bit is set for the Flash Erase Cycles. This does<sattarhastam> 在 2025-05-24 上传 | 大小:1kb | 下载:0