[VHDL编程] aescore

说明：基于FPGA的AES算法实现的VERILOG源代码，对于信息安全专业研究AES算法的硬件实现很有用-FPGA-based AES algorithm implementation VERILOG source code, for the information security professional research of the hardware implementation of AES algorithm is useful
<李华> 在 2025-11-19 上传 | 大小：191kb | 下载：0

[Windows CE] Draw

说明：evc4.0 用c++ 写的一个小画图程序,可以选择不同的颜色画一些简单的图案-evc4.0 using c++ to write a small drawing program, you can choose a different color painting simple patterns
<jiadongyue> 在 2025-11-19 上传 | 大小：3.01mb | 下载：0

[VHDL编程] tut_simulation_verilog

说明：This tutorial introduces the basic features of the QuartusII Simulator.
<Nguyen Chi Nhan> 在 2025-11-19 上传 | 大小：294kb | 下载：0

[其他嵌入式/单片机内容] avm

说明：关于温度采集并用数码管显示显示系统的课程设计。-With regard to temperature acquisition and use of digital tube display system for curriculum design.
<juyong> 在 2025-11-19 上传 | 大小：1kb | 下载：0

[其他嵌入式/单片机内容] MAIN

说明：this a file used for the spi communication between spi1 and spi2 of dspic30f6014. this is the main file which is heart of this project.-this is a file used for the spi communication between spi1 and spi2 of dspic30f6014. this is the main file
<valiantyasir> 在 2025-11-19 上传 | 大小：1kb | 下载：0

[其他嵌入式/单片机内容] delay

说明：this a file used for the spi communication between spi1 and spi2 of dspic30f6014. this file is used for delay.-this is a file used for the spi communication between spi1 and spi2 of dspic30f6014. this file is used for delay.
<valiantyasir> 在 2025-11-19 上传 | 大小：1kb | 下载：0

[其他嵌入式/单片机内容] SPI_SLAVE

说明：this a file used for the spi communication between spi1 and spi2 of dspic30f6014. this file is for slave .-this is a file used for the spi communication between spi1 and spi2 of dspic30f6014. this file is for slave .
<valiantyasir> 在 2025-11-19 上传 | 大小：1kb | 下载：0

[其他嵌入式/单片机内容] SPI_MASTER

说明：this a file used for the spi communication between spi1 and spi2 of dspic30f6014. this file is used for spi master-this is a file used for the spi communication between spi1 and spi2 of dspic30f6014. this file is used for spi master
<valiantyasir> 在 2025-11-19 上传 | 大小：2kb | 下载：0

[VHDL编程] SequentialCircuitDesign_withVerilog

说明：Verilog source code is usually typed into one or more text files on a computer. Those text files are then submitted to a Verilog compiler or interpreter which builds the data files necessary for simulation or synthesis. Sometimes simulation imm
<Nguyen Chi Nhan> 在 2025-11-19 上传 | 大小：292kb | 下载：0

[VHDL编程] tut_quartus_intro_verilog

说明：Verilog source code is usually typed into one or more text files on a computer. Those text files are then submitted to a Verilog compiler or interpreter which builds the data files necessary for simulation or synthesis. Sometimes simulation imm
<Nguyen Chi Nhan> 在 2025-11-19 上传 | 大小：800kb | 下载：0

[VHDL编程] tut_timing_verilog

说明：Verilog source code is usually typed into one or more text files on a computer. Those text files are then submitted to a Verilog compiler or interpreter which builds the data files necessary for simulation or synthesis. Sometimes simulation imm
<Nguyen Chi Nhan> 在 2025-11-19 上传 | 大小：361kb | 下载：0

[其他嵌入式/单片机内容] LCDdisplay

说明：this a file used for the spi communication between spi1 and spi2 of dspic30f6014. this file is the lcd file to display the communication between two spis.-this is a file used for the spi communication between spi1 and spi2 of dspic30f6014. this f
<valiantyasir> 在 2025-11-19 上传 | 大小：2kb | 下载：0