资源列表
[VHDL编程] cnt8bc
说明:8位加减带异步复位计数器,使用双向输入管脚- Design an 8-bit up and down synchronous counter in VHDL with the following features: The same ports are used for signals to be inputted and outputted. The ports are bi-directionally buffered. The counter is with an asynchro<fjmwu> 在 2025-06-10 上传 | 大小:1kb | 下载:0
[VHDL编程] FSMwithOutputsDecode
说明:有限状态机FSM with Outputs Decoded in Parallel Output Register-FSM with Outputs Decoded in Parallel Output Register<fjmwu> 在 2025-06-10 上传 | 大小:1kb | 下载:0
[VHDL编程] FSMwithOutputsEncodedwithinStateBits
说明:FSM有限状态机FSM with Outputs Encoded within State Bits-FSM with Outputs Encoded within State Bits<fjmwu> 在 2025-06-10 上传 | 大小:1kb | 下载:0
[VHDL编程] HighSpeedFIFOsInSpartan-IIFPGAs
说明:This application note describes how to build high-speed FIFOs using the Block SelectRAM+ memory in the Spartan™ -II FPGAs. Verilog and VHDL code is available for the design. The design is for a 512x8 FIFO, but each port structure can be chan<fjmwu> 在 2025-06-10 上传 | 大小:30kb | 下载:0