资源列表
[VHDL编程] HDB3
说明：基于FPGA的HDB3码的译码器代码，主要用于译码器-HDB3 yards on FPGA decoder code, mainly for the decoder<cenmingcan> 在 2025-06-27 上传 | 大小：1kb | 下载：0
[VHDL编程] i2c_master_slave_core_latest.tar
说明：This design is Wishbone compatible I2C core. This core can work as I2C master as well as slave. VMM Test-bench is also available.<Andrey> 在 2025-06-27 上传 | 大小：4.35mb | 下载：0
[VHDL编程] tiny64_latest.tar
说明：Descr iption Tiny64 A 64-Bit RISC CPU with minial resource usage. Every opcode is executed in 2 clock cycles. The word size is configurable via XLEN from 32 up to the FPGA limit. The assembler supports also differnet word sizes. Due simpli<Andrey> 在 2025-06-27 上传 | 大小：22kb | 下载：0
[VHDL编程] can_latest.tar
说明：Controller Area Network or CAN is a control network protocol from Bosch that has found wide use in Industrial Automation and the Automotive Industry. Most of the patents of CAN are owned by Bosch and although there are no restictions on de<Andrey> 在 2025-06-27 上传 | 大小：1.12mb | 下载：0
[VHDL编程] a_vhd_16550_uart_latest.tar
说明：A UART that is compatible with the industry standard 16550D Includes wrappers for the Wishbone and AMBA APB busses<Andrey> 在 2025-06-27 上传 | 大小：117kb | 下载：0
[VHDL编程] usb1_funct_latest.tar
说明：USB 1.1 slave/device IP core. Default configuration is 6 endpoints: 1 Control, 1 Isochronous IN, 1, Isochronous Out, 1 Bulk IN, 1 Bulk Out, 1 Interrupt IN. Includes control engine, providing full enumeration process in hardware - no external mi<Andrey> 在 2025-06-27 上传 | 大小：58kb | 下载：1