资源列表
[VHDL编程] VerilogCode_time_of_day_clock
说明:Verilog Code for time-of-day clock and it is implemented on Altera DE2 board-Verilog Code for time-of-day clock and it is implemented on Altera DE2 board<Rahul> 在 2025-06-24 上传 | 大小:2kb | 下载:0
[VHDL编程] sw_led
说明:一个关于fpga应用的程序,可以帮助初学者较快进入fpga的编程设计。程序比较简单,便于理解,实现了按键识别并点亮相应的数码管-An application program on the fpga, fpga to help beginners quickly into the programming design. Procedure is relatively simple, easy to understand, identify and implement key correspondi<马腾> 在 2025-06-24 上传 | 大小:214kb | 下载:0
[VHDL编程] modelism-simulink
说明:Modelsim simulation elementary guidance -Modelsim simulation elementary guidance<松竹> 在 2025-06-24 上传 | 大小:225kb | 下载:0
[VHDL编程] MODELSIMFANGZHEN(xilinxISE)
说明:MODELSIM仿真(适合xilinx ISE).pdf,硬件开发,FPGA相关,学习学习-MODELSIM simulation (for xilinx ISE). Pdf, hardware development, FPGA-related, learning to learn<hong> 在 2025-06-24 上传 | 大小:269kb | 下载:0
[VHDL编程] yy
说明:七人表决器当选举人大于或等于4时为通过,绿灯亮;反之不通过时,黄灯亮。描述时,只须检查每一个输入的状态(通过为“1”,不通过为“0”),并将这些状态值相加,判断状态值和即可选择输出。-Seven voting machines when voters is greater than or equal to 4 through the green light the other hand does not pass, the yellow light. Descr iption, just ch<黄国猛> 在 2025-06-24 上传 | 大小:29kb | 下载:0