资源列表
[VHDL编程] Bus_Enable
说明：veilog小程序 参考设计中的 该程序说明了如何使用一个总线-veilog applet reference design of the program shows how to use a bus<wop636> 在 2025-06-08 上传 | 大小：119kb | 下载：0
[VHDL编程] CoreFIR_RTL-3.0
说明：actelIP核 的fircore Core Generator – Executable File Outputs Run-Time Library (RTL) Code and Testbench Based on Input Parameters – Self-Checking – Executable Tests Generated Output against Algorithm • Distributed Arithmetic (DA) Algori<睿宸> 在 2025-06-08 上传 | 大小：1mb | 下载：0
[VHDL编程] I2s
说明：i2cSlave is a minimalist I2C slave IP core that provides the basic fr a mework for the implementation of custom I2C slave devices. The core provides a means to read and write up to 256 8-byte registers. These registers can be connected to the use<睿宸> 在 2025-06-08 上传 | 大小：181kb | 下载：0
[VHDL编程] MP3-coder
说明：In this design, it is assumed that a buffer sized as 1024x8 bits provides main data including scale factors and Huffman code bits to Huffman decoder. Also, it is assumed that a memory with 1024x8 bits is ready for each component to write or read t<睿宸> 在 2025-06-08 上传 | 大小：36kb | 下载：0
[VHDL编程] stopwatch-VHDL
说明：自己用VHDL语言写的一个秒表程序，包括秒，分秒和百分秒。有程序说明和VHDL代码，一看就懂-Own use VHDL language used to write a stopwatch program, including the seconds, minutes and seconds and hundredths of a second. There descr iption of the procedures and VHDL code, one can understand<conley> 在 2025-06-08 上传 | 大小：179kb | 下载：0