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[VHDL编程] simple
说明: 一个简单的8位处理器完整设计过程及verilog代码,适合初 学ic设计的人用,并含有我个人写的指令执行过程,仅供参 考-A simple 8-bit processor and the complete design process verilog code, suitable for beginners ic design for human use, and contains my personal writing instruction execution, for ref<lijinpeng> 在 2025-06-23 上传 | 大小:80kb | 下载:0
[VHDL编程] pipeline_mips_simulation_using_xilinx
说明:This project is a pipeline simulator using xilinx. All of fetch, decode, execute and write back stages was implemented. That is a nice project for computer architecture course in computer engineering. Good Luck ) -This project is a pipeline simul<Fartab> 在 2025-06-23 上传 | 大小:729kb | 下载:0