[VHDL编程] COMB

说明：We use port map statement to achieve the structural model (components instantiations). The following example shows how to write the program to incorporate multiple components in the design of a more complex circuit. In order to simulate the design, a
<sam> 在 2025-06-22 上传 | 大小：1kb | 下载：0

[VHDL编程] CALIBRATION

说明：Calibration is a comparison between measurements – one of known magnitude or correctness made or set with one device and another measurement made in as similar a way as possible with a second device. The device with the known or assigned correctness
<GOPALAKRISHNAN E> 在 2025-06-22 上传 | 大小：1kb | 下载：0

[VHDL编程] all-code-files

说明：code for virus detection processor in vhdl
<kusumanchi> 在 2025-06-22 上传 | 大小：17kb | 下载：0

[VHDL编程] finalcode

说明：vhdl code for simple virus detection processor. it can also develop in verilog
<kusumanchi> 在 2025-06-22 上传 | 大小：14kb | 下载：0

[VHDL编程] d-Flip-Flop

说明：D flip flop and some other codes added together recomended use is adding layer not use in a single bench
<Dou> 在 2025-06-22 上传 | 大小：2kb | 下载：0

[VHDL编程] mux8to1_with_if

说明：this code to input 8 different data and make them out sequentialy -this code to input 8 different data and make them out sequentialy
<freaker> 在 2025-06-22 上传 | 大小：18kb | 下载：0

[VHDL编程] Projects

说明：this is sub and adder in vhdl &writed in ISE
<mohammad> 在 2025-06-22 上传 | 大小：1kb | 下载：0

[VHDL编程] verilog-mode

说明：verilog mode for gvim
<tguy99999> 在 2025-06-22 上传 | 大小：91kb | 下载：0

[VHDL编程] UVM_Guidlines

说明：UVM Coding Guidelines for verification
<tguy99999> 在 2025-06-22 上传 | 大小：63kb | 下载：0

[VHDL编程] ahb_master

说明：AHB master system generator in verilog
<Prashanth R> 在 2025-06-22 上传 | 大小：9kb | 下载：0

[VHDL编程] Array-multiplier

说明：Array muiltiplier verilog code.. 4 bit two inputs with 8 bit outputs
<Prashanth R> 在 2025-06-22 上传 | 大小：1kb | 下载：0

[VHDL编程] pid

说明：pid controller design based vhdl code in xilinx code-pid controller design based vhdl code in xilinx code.....................
<GOPALAKRISHNAN E> 在 2025-06-22 上传 | 大小：1kb | 下载：0